[register]-05-Detailed explanation of commonly used system registers in ARMv8

PSTATE: Program Status Register

SP_ELx(x>0): In EL1/EL2/EL3 level, if spsel=0, use SP_ELx(x>0)

SP_EL0: In all levels, if spsel=1, use SP_EL0

SPSR: save program status register backup program status register

ELR_ELx (x>0): Exception link register, which records the return address of the program when an exception occurs

ESR_ELx(x>0): Synchronous exception, exception characteristic register

FAR_ELx(x>0): Synchronous exception, error address at the time of exception

VBAR_ELx (x>0): Vector table base address register

TTBRn_ELx (n=1,2, x>0): Address translation base address register

MAIR_ELx(x>0): Memory attribute register

PAR_EL1: Physical address register. When the instruction is used to operate the MMU to convert VA to PA, the physical address is output by PAR_EL1.

SCR_EL3: Security Configuration Register

SCTLR_ELx(x>0): System control register

TCR_ELx(x>0): Address translation control register

1、PSTATES

PSTATE bit definition:

（1）、spsel : (Stack Pointer Select)

2. Introduction to Stack pointer (sp) register

By default, when an exception occurs, the sp of the current exception level is selected. For example, if an exception occurs to EL1, sp_el1 will be automatically selected as the sp;

However, at high exception levels, you can also use SP_EL0 by modifying spsel

3、SCR_EL3 ：（Secure Configuration Register）

NS ：0-secure state, 1-NonSecure state

IRQ: 0-IRQ will not target EL3 when running below EL3, 1-IRQ will always target EL3

FIQ: 0-fiq will not target EL3 when running below EL3, 1-fiq will always target EL3

EA, bit [3] :

– 0- When running below EL3, External aborts and SError will not target EL3. When running in EL3, Serror will not be generated, and External aborts target EL3

– 1-External aborts and SError target到EL3

SMD, bit [7]: 0-smc instruction is enabled in EL3/EL2/EL1, 1-smc instruction is disabled

HCE, bit [8]: 1-hvc instruction is enabled in EL3/EL2/EL1, 0-hvc instruction is disabled

4、SCTLR：（System Control Register）

whether...or)

UCI: When set to 1, EL0 can access DC CVAU, DC CIVAC, DC CVAC, IC IVAU instructions under aarch64.

EE：0-Little endian， 1-Big endian.

EOE: Data access mode displayed by EL0, 0-Little endian, 1-Big endian.

WXN: 0-XN permission is not enabled, XN permission is enabled

nTWE: 1-WFE is a normal instruction

nTWI: 1-WFI is a normal instruction

UCT:1- EL0 can access CTR_EL0

DZE: 1-EL0 can access the DC ZVA instruction of the cache

I：Instruction cache enable

UMA: EL0 interrupt mask (for aarch64)

SED: 1-SETEND instruction disabled (for aarch32)

ITD: 1-IT command disabled

CP15BEN: cp15 enable (for aarch32)

SA0 Enable alignment checking at EL0sp

SA turns on sp alignment check

C ：data cache enable

A : alignment check enable

M ： enable MMU

Explanation of big and small end:

XN Permissions: