Realization of LED display screen based on single chip microcomputer and programmable logic device

0 Introduction

The LED display screen is mainly composed of three parts: current drive circuit and LED dot matrix array, control system and PC management software (Figure 1). The control system is responsible for receiving, converting and processing various external signals, and realizing scanning control, and then driving the LED dot matrix to display the required text or pattern. As the core part of the LED display screen, the control system directly determines the display effect and performance of the display screen. This article analyzes in detail the use of Verilog HDL to program ATF1508AS to achieve dual-port RAM access and generate various timing signals required by the LED dot matrix drive circuit.

1 Basic structure and key technologies of LED display

In this system design, the control system is implemented using a single-chip microcomputer + CPLD solution. The entire control system can be divided into: signal receiving and processing module, CPLD scanning control module and LED dot matrix drive module, as shown in Figure 1. The key technology of this system is the use of dual-port RAM and CPLD chips to solve the problem of high-speed data transmission and fast scanning control in the LED display screen, greatly improving the refresh rate of dynamic display.

The function of the signal receiving and processing module is that the AT89S52 microcontroller receives the dot matrix information sent by the PC through the serial port, and performs various processing on the dot matrix information. The dual-port RAM IDT7007 is used to establish a high-speed data exchange channel between the microcontroller and ATF1508AS in a shared manner.

The scanning control module of CPLD is implemented with ATF1508AS chip. Its function is to read dot matrix information from dual-port RAM, serialize it and send it to the display scanning drive circuit, and output various required control signals at the same time. CPLD has the characteristics of fast scanning speed and short delay, which overcomes the flickering effect caused by the slow transmission rate of the single-chip microcomputer when displayed on a large screen.

2 Design of Scan Control Module Based on CPLD

2.1 Design Concept

The function of this module is to read data from the memory, transmit the data to the display screen, and generate various control signals. The timing generation module consists of two parts: one is to generate the timing for accessing the dual-port RAM, and the other is to generate various signals required by the LED display interface.

For the hardware circuit, we use the more common CPLD chip ATF1508 to realize the timing generation part in the control system. CPLD is a programmable logic device with abundant programmable I/O pins. It can not only realize the conventional logic device functions, but also realize complex and unique timing logic functions. For the software, we use Verilog HDL language for design. Verilog HDL is a hardware description language for logic design and has become an IEEE standard. We use Verilog HDL language to program ATF1508AS to realize the functions required by the scan control module.

The principle circuit of the scan control part is shown in Figure 2. ATF1508AS is the core part. It is necessary to define the various I/O ports of ATF1508AS according to system requirements. The following is the Verilog HDL language code for I/O port definition and internal register definition.

module LedSequ(color, datain, addrout, CE, OE, SEMR, RWC, sdr, sdb, sck, le, oe1, cs, clk, counter);
input clk; //system clock
input[7:0] datain; //RAM data input
input[1:0] color; //color control
output[13:0] addrout; //address output port
output SEMR,RWC;
output CE,OE,sdr,sdb,sck,le,oe1,cs;
output[3:0] counter;
reg[3:0] hcnt; //38 decoder counter
reg [7:0] data1; //data register
reg[3:0] counter; //38 encoder output
reg SEMR,RWC;
reg SDA,SDC;

reg[13:0] addrout,addr;//addr address counter
reg[3:0] state;// status register
reg [2:0] shcnt; //shift pulse reader
reg CE,OE,sdr,sdb,sck,le,oe1,cs;
reg [8:0] byte;
parameter s0=1'd0,s1=1'd1,s2=1'd2,s3=1'd3, s4=1'd4, s5=1'd5; //state constant
2.2 Generation of timing for accessing dual-port RAM
IDT7007 is a dual-port RAM circuit with 32KB. The connection circuit with ATF1508AS is shown in Figure 2, where: is the chip select signal, is the read and write control signal, is the output enable signal, A0R-A13R is the right port address bus, D0R-D7R is the right port data bus, and its right port read and write timing is shown in Figure 4. We use a finite state machine to implement it. Its basic working principle is: S0 state is initialized, in S1 state ATF1508AS first outputs the address signal addrout, and then sets the phase to be valid, S2 state reads the data of the dual-port RAM and stores it in the content register datain, thus completing the dual-port RAM data reading process. The following is the main code for ATF1508AS to read dual-port RAM data:
always @ (posedge clk)
begin //The state changes once in each clock cycle
case(state)
s0: begin //Initialization state
CE=1'b0; //IDT7007 chip select
OE=1'b1; //IDT7007 read enable
le=1'b0;
oe1 = 1'b0;
cs = 1'b0;
addr= 14'b0;
SEMR=1'b1; //IDT7007 set to 1
RWC = 1'b1; //Write control 1
hcnt=4'b0000;
counter=4'b0000;
state=s1;
end
s1: begin //Output RAM address
CE=1'b0;
addrout=addr;//Output address
OE=1'b0;
SEMR=1'b1;
RWC = 1'b1;
shcnt = 3'b000;
state=s2;
end
s2: begin //Read dual-port RAM data
oe1=1'b0;
data1 = datain;
state=s3;
end
……(display scanning and LED drive code part)
endcase
end

2.3 Generation of LED display drive timing signals

The interface between CPLD and LED dot matrix driving circuit is shown in the figure, where: CS is the chip select signal of 3-8 decoder; OE is the output enable signal of BMI5026, which controls whether the LED dot matrix can be lit; LE is the data latch signal of the driver chip; sck is the shift pulse, which shifts the red and green data serially output by CPLD into MBI5026 (shift register); AD is the data input of the 4-16 decoder composed of dual 3-8 decoders, which realizes the display row selection control; sdr is the red data signal line; sdb is the green data signal line.
Its working process is as follows: in S3 state, sck pulse is set to 0, sdr and sdb output one bit of data respectively; in S4 state, sck is set to 1, red and green data are respectively shifted into corresponding shift register BMI5026, if less than 8 bits, return to S3 state, if less than one line, return to S1 state, read the next byte, if one line of data shifting process is completed, then turn to S5 state; in S5 state, le is set to 0, send the dot matrix data of one display line in the buffer of BMI5026 to the output register, and at the same time, cs1 is set to be valid to control the dot matrix display of the hcnt line, and then judge whether the display of one screen content is completed, and return to S1 state. Figure 4 is the state diagram of the complete finite state machine.

The following is the Verilog HDL program code corresponding to the LED display screen driving timing signal:

s3: begin
sck=1'b0;
sdr= SDA && color[0];
sdb= SDC && color[1];
OE=1'b1; CE=1'b1;
state=s4;
end
s4: begin // Shift and output to LED display
sck = 1'b1;
shcnt = shcnt +1'b1;
if (shcnt == 0)
begin
addr=addr+1'b1; //After reading a byte, the address counter increases by 1
byte=byte+8'b1;
if(byte= = nrow)// If a line of data is read
begin
oe1=1'b1;// Turn off LED display
cs=1'b1;
le=1'b0;// Write data to the driver chip
byte = 8'b0;
state=s5;// After reading a line of data, display it
end
else state=s1;
end
else state=s3; // Shift and output the current byte
end
s5: begin
sck=1'b0;
le=1'b0;
counter=hcnt;
OE=1'b1;
CE=1'b0;
if(addr = = nscreen)
addr=0;
oe1=1'b0;
cs=1'b0;
state =s1;
end

4 System testing and simulation

The development and debugging environment of the system is: the MCU part is debugged under KeilC51, and the CPLD part is debugged under Maxplus10. After the Verilog HDL source program of the scanning control module of the LED display is written, the software simulation can be performed in ALTERA's Maxplus10 to observe whether each signal meets the timing requirements of the hardware circuit. Figure 5 shows the simulation results of the scanning module CLPD, which meets the design requirements. After downloading to ATF1508AS through the JTAG interface, the system works normally.

5 Conclusion

The LED display scanning control module implemented based on Verilog HDL is used in our development of LED large-screen electronic information display system, which simplifies the system structure and improves the cost performance. The LED display has good display effect in practical application, clear picture and stable performance, and has been applied in many departments of the school.