ATmega48 EEPROM Data Memory

ATmega48/88/168 contains 256/512/512 bytes of EEPROM data memory. It is used as a separate data EEPROM with a life of at least 100,000 erase cycles. EEPROM access is determined by the address register, data register and control register.

For specific SPI and parallel download EEPROM data, please refer to P254 "Memory Programming".

EEPROM Read/Write Access

EEPROM Read/Write Access The EEPROM access register is located in the I/O space.

The EEPROM write access time is given in Table 3. The self-timing function allows the user software to monitor when it can start writing the next byte. Users need to pay attention to the following issues when operating the EEPROM: In circuits with a relatively large power filter time constant, the VCC rise/fall speed will be slower during power-on/power-off. At this time, the CPU may be operating at a power supply voltage lower than the crystal oscillator required. Please refer to P20 "Preventing EEPROM Data Loss" to avoid EEPROM data loss.

In order to prevent unintentional EEPROM write operations, a specific write sequence needs to be executed. For details, refer to the contents of the EEPROM control register.

When performing an EEPROM read operation, the CPU will stop working for 4 cycles before executing subsequent instructions; when performing an EEPROM write operation, the CPU will stop working for 2 cycles before executing subsequent instructions.

EEPROM address registers - EEARH and EEARL

· Bits 15..9 – Res: Reserved
bits, read operations return a value of zero.

· Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the 256/512/512 bytes of EEPROM.
The EEPROM address is linear, from 0 to 255/511/511. The initial value of EEAR is undefined. The EEPROM must be assigned the correct data before accessing it.
EEAR8 is an invalid bit in the ATmega48 and must always be assigned a value of "0".

EEPROM Data Register – EEDR

· Bits 7..0 – EEDR7.0: EEPROM data
For EEPROM write operations, EEDR is the data to be written to the EEAR location; for read operations, EEDR is the data to be read from address EEAR.

EEPROM Control Register - EECR

· Bits 7..4 – Res: Reserved
Reserved bits, read operations return a value of zero.

· Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming Mode bits determine what programming mode will be triggered after writing to EEPE. EEPROM programming can be performed as an atomic operation to erase old data and write new data, or it can be performed in two steps. The timing of the different programming modes is shown in Table 2. When EEPE is set, any write operation to EEPMn will be ignored. During reset, unless the EEPROM is in the programming state, the EEPMn bits will be set to 0b00.

· Bit 3 – EERIE: Enable EEPROM ready interrupt
If I of SREG is "1", setting EERIE enables the EEPROM ready interrupt. Clearing EERIE disables this interrupt. The EEPROM ready interrupt occurs when EEPE is cleared.

· Bit 2 – EEMPE: EEPROM write enable
EEMPE determines whether setting EEPE to "1" can start the EEPROM write operation. When EEMPE is "1", setting EEPE to "1" within 4 clock cycles will write data to the specified address of the EEPROM; if EEMPE is "0", EEPE has no effect. Four cycles after EEMPE is set, it is cleared by hardware. See the description of the EEPE bit in the EEPROM write process.
· Bit 1 – EEPE: EEPROM write enable
The write enable signal EEPE is the write select signal of the EEPROM. After the EEPROM data and address are set, EEPE needs to be set to write data to the EEPROM. At this time, EEMPE must be set, otherwise the EEPROM write operation will not occur. The write sequence is as follows (the order of steps 3 and 4 can be changed):
1. Wait for the EEPE bit to become zero
2. Wait for the SPMEN bit in the SPMCSR to become zero
3. Write the new EEPROM address to EEAR (optional)
4. Write the new EEPROM data to EEDR (optional)
5. Write "1" to EEMPE in the EECR register and clear EEPE at the same time
6. Within 4 cycles of setting EEMPE, set EEPE

to prevent the EEPROM from being programmed while the CPU is writing to the Flash memory. The software must check whether the Flash write operation has been completed before starting the EEPROM write operation. The second step is only useful if the software contains a bootloader that allows the CPU to program the Flash. If the CPU will never write to the Flash, the second step can be ignored. Please refer to P240 “Boot Loader Supports RWW Self-Programming, ATmega88 and ATmega168”. (Note: ATmega48 does not have a Boot Loader)

Note: If an interrupt occurs between steps 5 and 6, the write operation will fail. This is because the EEPROM write enable operation will time out. If an interrupt to an EEPROM operation interrupts another EEPROM operation, the EEAR or EEDR register may be modified, causing the EEPROM operation to fail. It is recommended to turn off the global interrupt flag I at this time.

After the write access time, EEPE is cleared by hardware. The user can use this bit to determine whether the write timing has been completed. After EEPE is set, the CPU will stop for two clock cycles before running the next instruction.

Bit 0 – EERE: EEPROM Read Enable The
read enable signal EERE is the write enable signal for the EEPROM. After the EEPROM address is set, EERE must be set to read data into EEAR. Reading EEPROM data only requires one instruction. When reading EEPROM, the CPU stops for 4 clock cycles before executing the next instruction.

The user should check EEPE when reading EEPROM. If a write operation is in progress, the EEPROM cannot be read and the register EEAR cannot be changed. The calibrated on-chip oscillator is used for EEPROM timing.

The calibrated oscillator is used for EEPROM access timing. Table 3 shows the typical time for CPU to access EEPROM.

The following code uses assembly and C functions to illustrate how to implement EEPROM write operations. It is assumed that interrupts will not occur during the execution of these functions. The example also assumes that the software does not have a boot program. If a boot program exists, the EEPROM write function needs to wait for the completion of the ongoing SPM command.

Assembly code routine
EEPROM_write:
; Wait for the previous write operation to complete
sbic EECR,EEPE
rjmp EEPROM_write
; Set address register (r18:r17)
out EEARH, r18
out EEARL, r17
; Write data to data register (r16)
out EEDR,r16
; Set EEMPE
sbi EECR,EEMPE
; Set EEPE to start write operation
sbi EECR,EEPE
ret
C code routine
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for the previous write operation to complete */
while(EECR & (1<;
/* Set address and data registers */
EEAR = uiAddress;
EEDR = ucData;
/* Set EEMPE */
EECR |= (1</* Set EEPE To start the write operation */
EECR |= (1<} 

The following example shows how to read the EEPROM using assembly and C functions, assuming that interrupts will not occur during the execution of these functions.

Assembly Code Routine
EEPROM_read:
; Wait for the previous write operation to complete
sbic EECR,EEPE
rjmp EEPROM_read
; Set address register (r18:r17)
out EEARH, r18
out EEARL, r17
; Set EERE to start a read operation
sbi EECR,EERE
; Read data from data register
in r16,EEDR
ret
C Code Routine
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for the previous write operation to complete*/
while(EECR & (1<;
/* Set address register*/
EEAR = uiAddress;
/* Set EERE to start a read operation*/
EECR |= (1</* Return data from data register*/
return EEDR;
} 

EEPROM write operation in power-down sleep mode

If the EEPROM write operation is in progress when the program executes the power-down instruction, the EEPROM write operation will continue and be completed before the specified write access time. However, after the write operation is completed, the oscillator will continue to run, and the microcontroller is not in a complete power-down mode. Therefore, the EEPROM write operation should be terminated before executing the power-down instruction.

Prevent EEPROM data loss

If the power supply voltage is too low, the CPU and EEPROM may not work properly, causing EEPROM data to be destroyed (lost). This situation will also be encountered when using independent EEPROM devices. Therefore, the same protection scheme needs to be used.

There are two possibilities for EEPROM data damage due to low voltage: one is that the voltage is lower than the minimum voltage required for EEPROM write operation; the other is that the CPU itself can no longer work properly.

The problem of EEPROM data damage can be solved by the following method:
keep the AVR RESET signal low when the voltage is too low. This can be achieved by enabling the chip's power-off detection circuit BOD. If the BOD level cannot meet the requirements, an external reset circuit can be used. If a reset occurs during the write operation, the write operation will still end normally as long as the voltage is high enough.