S3C2440—4. Clock system

1. Introduction to S3C2440 clock system

1. Bus and clock

S3C2440 has two buses: AHB high-speed bus and APB peripheral bus.

Corresponding to three clock sources:

FCLK of ARM chip CPU

HCLK of AHB bus

PCLK of APB bus

The operating frequencies of the three clocks are:

(It can be seen that compared with the 72MHz frequency in STM32, the performance of the ARM clock has been greatly improved)

2. Clock source

How to get the three clocks? The system clock source is a 12MHz crystal oscillator. Through the PLL phase-locked loop hardware device, a clock frequency of up to 400MHz can be obtained. The clock block diagram is as follows:

It can be seen that there are two options for system clock sources:

Crystal Oscillator

External Input

(Only crystal oscillator is discussed here)

3. Select the clock

The clock source can be selected by setting OM[3:2].

Here’s how to set it up:

Open the schematic diagram to check the current status of OM[3:2] (check the current clock source selection)

It can be seen that OM[3:2] are both grounded, that is, OM[3:2]=00, so the clock source is a 12MHz crystal oscillator.

4. Generate clock

Therefore, the three clocks FCLK, HCLK and PCLK are all generated by the crystal oscillator.

The clock frequency provided by the crystal oscillator is converted into a new clock frequency through MPLL and UPLL

MPLL: main PLL, using P[5:0], M[7:0], S[1:0] to control the frequency of the output clock

UPLL: USB PLL, using P[5:0], M[7:0], S[1:0] to control the frequency of the output clock

The block diagram is as follows:

The crystal oscillator signal passes through the MPLL to generate a clock as FCLK (400MHz) and is provided to the CPU. FCLK then passes through the divider to generate HCLK (136MHz) and PCLK (68MHz).

FCLK is provided to the CPU (ARM920T)

HCLK is provided to various AHB buses (high-speed devices): Nand FLASH, ITC, Memory Controller...

PCLK is provided to various APB buses (low-speed devices): IIC, IIS, GPIO, ADC...

Therefore, the crystal oscillator passes through MPLL to obtain FCLK, and FCLK is divided to obtain HCLK and PCLK.

5. Process

After power-on, the reset pin will be maintained for a period of time to wait for the power supply to stabilize, and the reset pin is maintained by a dedicated reset chip:

The reset pin will output a high level after a period of time after power-on.

At the beginning, the FCLK frequency is directly provided by the crystal frequency, because the CPU is not working (not reset) at this time. When the PLL latches the value of OM[3:2], the CPU starts running and starts to set the PLL. During the setting, the CPU stops (Lock Time). After the PLL setting is completed, FCLK is the new frequency:

2. How to configure the clock source

Configuring the clock source mainly involves operating two registers:

MPLLCON

CLKDIVN

1. Set the FCLK frequency register MPLLCON

Control the MPLL output FCLK clock frequency

You can refer to the standards given in the manual:

The calculation formula of MPLL is:

2. Set the frequency division HDIV, PDIV register CLKDIVN

3. Clock switch control register CLKCON

Control the clock on and off of certain modules

Notice: