1.5.3_undException mode program example

When the CPU executes an undefined instruction, an undefined instruction exception is triggered.

Through the exception vector table, we can find that the entry of the undefined instruction exception is at 0x0000,0004. That is, when the CPU executes the undefined instruction exception, the CPU on the hardware will jump to 0x0000,0004 to execute the code.

We trigger the exception by deliberately adding an undefined instruction 0x0300,00000 in the code. The figure below is the structure of a normal instruction. The original figure has the bit marks reversed, and the left to right should be 31-0.

The following table is a description table of interrupt exit and entry. It can be seen from the table that under ARM instructions, before entering the undefined instruction exception, the address of PC+4 will be stored in R14_x, which is lr_und, so when exiting, you only need to pass R14_und to PC.

When handling an undefined instruction exception, we first store the values ​​of the r0-r12 registers on the stack, and then store the value of the lr_exception on the stack. Because these values ​​may be modified, they must be saved first.

The functional definition of the registers is as follows.

After saving the scene, we perform exception handling. In the exception handling function, we print out the cpsr and output an additional string to indicate that an undefined instruction exception has occurred.

The .string directive is used to define the string here. The difference between it and the .ascii directive is that the string defined by the .ascii directive will not automatically add an end character at the end, while the string defined by the .string directive will automatically add an end character.

The following figure is a schematic diagram of the sequence of handling undefined instruction exceptions. After power-on, the CPU starts executing from address 0, then relocates and copies the entire code to SDRAM and jumps to SDRAM for execution. When an undefined instruction is detected, an exception is triggered and jumps back to 0x4, and then jumps to SDRAM at 0x4 to handle the undefined instruction exception.