Interface Design between Single Chip Microcomputer 89C51 and A/D Converter MAX195

MAX195 is a 16-bit successive approximation ADC. It combines high accuracy, high speed, low power consumption (current consumption is only 10μA) and shutdown mode. The internal calibration circuit corrects linearity and offset errors, so all rated performance indicators can be achieved without external adjustment. The capacitive DAC structure gives it a unique 85kbps track/hold function, and the conversion time is only 9.4μs. The three-state serial data output and pin-selectable unipolar (0~VREF) or bipolar (-VREF~+VREF) input range make it widely used in portable instruments, medical signal acquisition and multi-sensor measurement systems.

1 MAX195 Pinout and Description

MAX195 has 16 pins, which are arranged as shown in Figure 1.

2 MAX195 conversion principle and timing

The MAX195 chip contains a capacitive digital-to-analog converter (DAC) that can track and hold the analog input. The successive approximation register and comparator, under the control of the conversion clock CLK, convert the analog input into a 16-bit digital code and output it through the serial interface on the chip. The interface and control logic on the chip are easily connected to most microprocessors, reducing the need for external components.

The timing of its transformation and data output is shown in Figure 2.

It can be seen from the timing that the conversion starts at the effective CLK falling edge after at least three or more clock cycles have passed since the previous conversion ended (MAX195 requires 4 CLK cycles to track/hold and collect signals). At the same time, it becomes high at the next clock falling edge, and after 9.4μs (CLK is 1.7MHz) after the conversion is completed, it changes from high to low, giving a conversion end signal, which can be sent to an interrupt or be queried. The conversion end is output by the three-state serial port DOUT. During the conversion, the data is read out by CLK control, and the data can also be read out by the SCLK serial clock between two conversions. The maximum rate can reach 5Mbps. The latter is shown in Figure 2. After maintaining a low level, at each falling edge of SCLK, the DOUT terminal outputs one bit of data in the order of MSB first, otherwise, DOUT is in a high impedance state.

3 MAX195 Calibration

The MAX195 is automatically calibrated at power-up. To reduce the effects of noise, each calibration test is performed multiple times and the results are averaged. At a clock frequency of 1.7MHz, calibration takes approximately 14,000 clock cycles or 8.2ms. In addition to power-up calibration, pulling OUT to a low level will suspend the MAX195, and returning OUT to a high level will start a new calibration.

Note: Recalibration is only recommended when starting power-on calibration during the power-on delay period when the power supply has not yet stabilized or when there are significant changes in power supply voltage, ambient temperature, and clock frequency.

The software calibration reference subroutine is as follows:

4 Interface Design between AT89C51 and MAX195

Figure 3 is the hardware circuit diagram of the interface between AT89C51 and MAX195.

In the figure, the ALE output signal of AT89C51 (equal to 1/6 crystal frequency fosc = 6MHz) is used as CLK conversion clock. P1.5 is used as the start control terminal of MAX195. The terminal is left floating to indicate that the analog signal can be bipolar input, or it can be connected to +5V as needed, which is a unipolar input; grounding, which is a shutdown mode.

According to Figure 3, the A/D sampling procedure is given as follows:

Note: The sampling results are saved in R2 and R33.