Understanding Delta-Sigma (Δ) ADCs

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Understanding Delta-Sigma (Δ) ADCs [Copy link]

As discussed in Part 1, the analog sensor signal chain faces high-precision challenges: multiple gain, signal conditioning, and complex analog filtering stages, all feeding the SAR-ADC; thus, analog errors may result. Designers may also end up with an expensive, component-dense PC board solution.

Furthermore, starting with very low sensor signals, the output of each analog stage in the signal chain generates errors, which manifest as low signal-to-noise ratio (SNR) and high distortion errors at the digital output of the converter. Designers of such systems need to take a step back and rethink the high-precision sensor ADC paradigm.
To address the issues associated with high-precision sensor systems, an ADC topology is chosen that quickly digitizes small sensor signals and digitally implements noisy analog functions such as gain and filtering. This is where the delta-sigma (Δ) ADC comes in.
This article briefly introduces the basic functionality of the Δ ADC and the internal analog-to-digital conversion mechanism, using the AD4110-1 universal input analog-to-digital front end from Analog Devices as an example. From there, the article dives into the surrounding signal chain and provides some key specifications for a suitable data acquisition system.

Structure of the Δ ADC

Just before the turn of the century, the Δ ADC usurped the dominance of analog technology. As Δ advanced technology became more widespread, primarily analog signals and computational processes began to take root in the digital realm. An examination of a Δ ADC integrated circuit (IC) reveals that more than 80% of the silicon real estate is used to perform digital functions. The byproducts of the predominantly digital circuitry are robustness and small size.
How was this possible? It started with direct digitization of low-voltage analog signals. Once in the digital realm, digital circuits were able to almost completely replace analog filtering while also performing any required gain functions (Figure 1). Digital circuits also shrunk with each semiconductor process node.

Figure 1: A Δ contains nearly all the necessary circuitry for filtering and gain. In this example, the Δ ADC senses and digitizes a small resistance temperature detector (RTD) voltage. It then uses internal digital signal gain and filtering to present a low-noise, 24-bit digital result. (Image source: A Baker's Dozen)
In Figure 1, the 24-bit Δ ADC system consists of an analog input, a central digital engine, and a digital I/O terminal. The converter takes the low-voltage RTD signal and produces a full 24-bit digital representation of the analog input through digital filtering. There is no analog gain block here that typically dominates SAR-ADC circuits, and the only analog filter is the combination of R1 and C1. Yes, this is a simple, inexpensive first-order filter!

How Δ ADCs Work
The basic topology of a Δ ADC has a Δ modulator in series with a digital filter. Most Δ ADCs have a variety of other features in addition to this basic topology. However, all Δ converters have this basic core (Figure 2).

Figure 2: In terms of basic elements, every Δ ADC has a Δ modulator, digital filter, and decimator. (Image source: EDN)
In Figure 2, the input can be either a sine wave or DC; here we will focus on the sine wave input. The Δ modulator digitizes a single cycle sine wave into a 1-bit stream. The Δ modulator output is sampled at a frequency Fs. Although the 1-bit modulator conversion appears to have high quantization noise, the signal noise has actually been “shaped” to a higher frequency. This paves the way for a low-noise, high-resolution conversion at the output of the digital filter.
At the output of the modulator, the digital filter accumulates the 1-bit result of the Δ modulator and performs the filter calculations. The digital filter output signal digitally reflects the analog input signal while continuing to be at the output frequency Fs. The signal now remains solely in the digital domain. A digital low-pass filter or decimation filter attenuates high frequency noise and slows down the output data rate by 1/Fd. The digital/decimation filter samples and filters the modulator’s 1-bit code stream into a slower, multi-bit code.
While most converters have only one sampling rate, the Δ converter has two: the input sampling frequency (Fs) and the output data frequency (Fd). According to Equation 1, the ratio of these two frequency variables defines the system decimation rate (DR):
Equation 1

Δ Modulator
The Δ modulator performs the actual analog-to-digital conversion by generating a 1-bit code stream. The process begins with the differential amplifier (Figure 3).

Figure 3: The Δ ADC modulator input stage detects the delta between the analog input and the feedback DAC. The second stage implements an integrator function (or integration) on the analog signal. (Image source: EDN)
In Figure 3, the differential amplifier (delta) transmits the analog signal to the integrator (integral). At the output of the integrator, a comparator differentiates the output of the integrator from a voltage reference (VREF) at a very high sampling rate (1/Fs). In addition, the comparator provides a 1-bit stream to a 1-bit digital-to-analog converter (DAC). The modulator then measures the difference between the analog input signal and the analog output of the feedback DAC.

Δ >The modulator shapes the noise to higher frequencies through the action of the integrator and DAC feedback loop. The formula in Figure 3 (lower right) shows the transfer equation: Yi = Xi-1 + (ei – ei-1). The modulator digitizes the input signal (Xi) into a 1-bit output code (Yi) through the quantization noise (ei). Specifically, the output of the modulator (Yi) is equal to the input (Xi-1) plus the quantization noise (ei – ei-1). The formula shows the quantization noise as the difference between the current error (ei) and the previous error of the modulator (ei-1).

Digital and Decimation Filters
Averaging is a form of digital filtering that is commonly used in low-speed industrial Δ ADCs. Almost all industrial Δ ADCs contain a type of averaging filter called a sinc filter, which uses a linear-phase finite impulse response (FIR), which is a type of digital low-pass filter (Figure 4).

Figure 4: The coefficients (bx) in this averaging FIR digital filter are all equal to 1. (Image source: Digi-Key Electronics)
In Figure 4, the modulator output bit stream is the input to this digital filter, and the modulator's sampling clock determines the delay time. The coefficients (bx) of the FIR filter in Figure 4 are all equal to 1. Using this averaging algorithm, the FIR digital filter produces a low-noise, 24-bit digital representation of the analog input in Figure 3, sampled at the modulator's sampling rate (1/Fs). The decimation filter then uses DR to reduce the output data rate.
In the literature, the term "decimation" refers to the military practice of systematically removing unwanted soldiers. In digital electronics, decimation uses the same concept to reduce the output data rate of a digital signal (1/Fd) through DR. The fast and digital way to do this is to systematically discard some of the digital filter's output samples (Figure 5).

Figure 5: The decimation process systematically reduces the number of digital 24-bit outputs by a factor of the output data rate (1/Fd, bottom of image) divided by the sampling rate (1/Fs). (Image source: Digi-Key Electronics)
Based on Equation 1, the decimation process in Figure 5 decimates the output data rate (1/Fd) by DR.
Events passing through the digital and decimation filters effectively reduce the Δ ADC noise (Figure 6).

Figure 6: Shown here is the digital filter output in the time domain (a); the modulator noise-shaped output superimposed on the decimation filter low-pass function (b); and the decimator output signal in the time domain (c). (Image source: EDN)
Figure 6 shows the digital signal as it passes through the digital/decimation filter. The digital filter’s 24-bit output (Figure 6(a)) runs at the same rate as the modulator sampling rate (1/Fs). The modulator has already shaped the quantization noise to higher frequencies (Figure 6(b)), so the digital/decimation filter captures the low-frequency portion of the output signal. The output of the decimation filter (Figure 6(c)) produces a low-frequency digital representation of the original analog signal.

Digital Extensions
The Δ ADC exists primarily in the digital domain. Now, digitally programmable gain stages, current sources, short-circuit or open-circuit input signal indicators, and a variety of serial output interfaces can be easily added (Figure 7).

Figure 7: The Analog Devices AD4110-1 provides a variety of analog front-end functions for industrial process control systems. (Image source: Analog Devices)
As shown in Figure 7, the Analog Devices AD4110-1 Δ ADC has many digital enhancements, including programmable input terminals, diagnostics, and flexible data rates. Input-ready sensor interfaces include RTD and thermocouple temperature sensors.
The AD4110-1 has the basic core of a Δ ADC, but the device’s digital emphasis supports a range of digitally enabled functions, making the AD4110-1 a general-purpose analog front end (AFE).
Like standard Δ ADCs, the AD4110-1 is capable of digitizing very low voltages from thermocouples, RTDs, and bridges. While these functions typically require additional excitation circuitry, the AD4110-1 has them integrated on the board.
For example, the RTD requires a precision current source that is ratiometric to the converter’s voltage reference (Figure 8).

Figure 8: Proper wiring connections for a four-wire RTD and the AD4110-1 Δ ADC. RTD excitation current can be programmed in six levels between 0.1 mA and 1 mA. (Image source: Analog Devices)
In Figure 8, the AD4110-1 includes an excitation current that can be programmed in six levels between 0.1 mA and 1 mA using the converter’s PGA_RTD_CTRL register. The excitation current for the RTD resistor comes from pin 35. The converter senses the voltage drop across the RTD via the pins 34 and 31 high impedance inputs. The AD4110-1 programmable gain amplifier (PGA) provides 16 programmable gains from 0.2 to 24 V/V. Using this feature, designers can further complement input sensors to the AD4110-1 input range. Other auxiliary features include pull-up/pull-down current to sense the presence of bare wire (useful for thermocouples), as well as gain calibration and correction factors.
Summary
The Δ ADC uses a front-end modulator, FIR digital filter, and decimation filter to eliminate complex analog front-end circuitry and provide a high-resolution, low-noise digital output signal that is digitally averaged. Since most of the circuitry is digital, it can be easily expanded with advanced digital process nodes to add more functionality while maintaining a small footprint and low board complexity.