ARM architecture/features (processors)

The ARM architecture supports implementations across multiple performance points and has become the dominant architecture in many market segments. The ARM architecture supports a very wide range of performance points, allowing extremely small ARM processor implementations and extremely efficient high-level design implementations to be achieved using the latest microarchitecture technologies. Implementation scale, performance and low power are key features of the ARM architecture.

ARM has developed architectural extensions to provide support for Java acceleration (Jazelle®), security (TrustZone®), SIMD and Advanced SIMD (NEON™) technologies. The ARMv8-A architecture adds cryptographic extensions as an optional feature.

The ARM architecture is similar to the Reduced Instruction Set Computing (RISC) architecture in that it contains the following typical RISC architectural features:

Unified register file load/store architecture, in which data processing operations are performed only on register contents and not directly on memory contents.

Simple addressing mode, all load/store addresses are determined only by register contents and instruction fields.

Enhancements to the basic RISC architecture allow ARM processors to achieve a good balance of higher performance, smaller code size, lower power consumption, and smaller silicon area.

A32 (ARM) architecture/features

ARM (often referred to as A32) is a fixed-length (32-bit) instruction set. It is the base 32-bit ISA used in the ARMv4T, ARMv5TEJ, and ARMv6 architectures. In these architectures, the instruction set is used in application areas that require high performance, or for handling hardware exceptions such as interrupts and processor startup.

For performance-critical applications and legacy code, the Cortex™-A and Cortex-R profiles of the Cortex architecture also support the ARM ISA. Most of its features are included in the Thumb instruction set introduced with Thumb-2 technology. Thumb (T32) benefits from improved code density.

ARM instructions are 32 bits long and need to be aligned on 4-byte boundaries.

Most ARM instructions can be "conditionalized" so that they are executed only if a previous instruction has set a certain condition code. This means that the instruction will only have its normal effect on the programmer's model operations, memory and coprocessors if the N, Z, C and V flags in the application status register satisfy the conditions specified in the instruction. If these flags do not satisfy this condition, the instruction acts as a NOP, i.e. execution proceeds normally to the next instruction (including any relevant checks for exceptions), but no other effects are taken. This conditionalization allows small parts of if and while statements to be encoded without the use of jump instructions.

Condition code N: Negative condition code, set to 1 if the result is negative

Condition code Z: Zero condition code, set to 1 if the result of the instruction is 0

Condition Code C: Carry condition code, set to 1 if the instruction generates a carry condition

Condition Code V: Overflow condition code, set to 1 if the instruction generates an overflow condition.

T32 (Thumb) Architecture/Features

Cost-sensitive embedded control applications such as cell phones, disk drives, modems, and pagers have been looking for ways to achieve 32-bit performance and address space at the lowest cost while trading off memory footprint.

The Thumb (T32) instruction set provides a subset of the most commonly used 32-bit ARM instructions compressed into 16-bit wide opcodes. At execution time, these 16-bit instructions are transparently decompressed into full 32-bit ARM instructions in real time with no performance loss.

Thumb provides designers with:

Excellent code density enables smallest system memory size and lowest cost.

Reduce system cost by achieving 32-bit performance in 8-bit or 16-bit memory on an 8-bit or 16-bit bus.

ARM functions built

Industry-leading MIPS/Watt to maximize battery life and maximize RISC performance

Small chip area to facilitate integration and minimize chip cost

Global multi-partner sources provide security assurance.

Designers can use both 16-bit Thumb and 32-bit ARM instruction sets simultaneously, giving them the flexibility to enhance performance or adjust code size at the subroutine level based on application requirements.

The Thumb ISA is widely supported by the ARM ecosystem, including a comprehensive Windows software development environment as well as development and evaluation cards.

Improved code density, performance efficiency and power efficiency

Thumb-2 technology makes Thumb a mixed (32-bit and 16-bit) length instruction set common to all ARMv7-compatible ARM Cortex implementations. Thumb-2 improves performance, power efficiency and code density for a wide range of embedded applications.

The technology is backward compatible with existing ARM and Thumb solutions, while significantly expanding the available functionality of the Thumb instruction set, allowing more applications to benefit from Thumb's best-in-class code density. For performance-optimized code, Thumb-2 technology uses 31% less memory to reduce system costs, while providing 38% higher performance than existing high-density code, so it can be used to extend battery life or enrich product feature sets.