51 MCU interrupt priority and interrupt nesting

Introduction: To put it simply, the old 51 MCU (80C51 series) has 5 interrupt sources, 2 priorities, and can implement two-level interrupt service nesting. Now many extended 51 MCUs have 4 priorities (or more) and more interrupt sources.

Before talking about interrupts, let me first define priority. If you understand what priority is, the following explanation will be easy to understand. In fact, many people confuse the meaning of priority, so they feel confused.

There are two interrupt priorities: query priority and execution priority.

What is the query priority? The default priority we see from the datasheet or book (IP register is not set, 00H after power-on reset) is:

External interrupt 0 > Timer/Event Counter 0 > External interrupt 1 > Timer/Event Counter 1 > Serial interrupt

or int0, timer0, int1, timer1, serial port or INT0, T0, INT1, T1, UART

Or PX0>PT0>PX1>PT1>PS>......

In fact, they are all query priorities. First of all, the query priority cannot be changed or set. This is a problem of interrupt priority queuing. It refers to the order in which the interrupt arbitrator chooses which interrupt source to prioritize when multiple interrupt sources generate interrupt signals at the same time. This has nothing to do with whether the interrupt service program is nested. When the CPU queries each interrupt flag bit, it will query it in sequence according to the above 5 query priority orders. When several interrupts are requested at the same time, the interrupt flag bit with a high query priority will be queried first, but it does not mean that the interrupt with a high query priority can interrupt the interrupt service with a low query priority that has been and is being executed.

For example: when the counter 0 interrupt and external interrupt 1 (according to the query priority, counter 0 interrupt > external interrupt 1) arrive at the same time, the interrupt service function of timer 0 will be entered; but when the interrupt service function of external interrupt 1 is being served, no interrupt can interrupt it at this time, including the external interrupt 0 counter 0 interrupt with a higher logical priority than it.

The execution priority of the interrupt is the setting of the IP register. In the case of 2 priorities, if a bit is 1, the corresponding interrupt source is high priority; if it is 0, it is low priority.

There are three principles regarding interrupt priority:

1. When the CPU receives several interrupts at the same time, it responds to the interrupt request with the highest priority first;

2. The ongoing interrupt process cannot be interrupted by a new interrupt request of the same or lower priority level;

3. The ongoing low priority interrupt service can be interrupted by a high priority interrupt request;

If: there is more than one interrupt request in the same execution priority, there is an interrupt priority queuing problem. The interrupt priority queuing of the same execution priority is formed by the natural priority determined by the interrupt system hardware. The order of priority from high to low is:

External interrupt 0>Timer/Counter 0>External interrupt 1>Timer/Counter 1>Serial interface

For example: Setting IP = 0x10, that is, setting the serial port interrupt as the highest priority, the serial port interrupt can interrupt any other interrupt service function to achieve nesting, and only the serial port interrupt can interrupt the service functions of other interrupts. If the serial port interrupt is not triggered, the other interrupts still maintain the logical priority and cannot be nested with each other.

Regarding interrupt nesting. It can be said that when an interrupt is being executed, if the interrupt priority register IP is set in advance, then when a higher priority interrupt arrives, interrupt nesting will occur. If it is not set, no nesting will occur. If an interrupt with the same priority is triggered, it is not "continuously applying", but its corresponding interrupt flag position, that is, a certain bit of the IE register, is set. After the CPU executes the current interrupt, it will re-query each interrupt flag bit according to the query priority and enter the corresponding interrupt.

Remember, when IP is not set, the MCU will queue up for service according to the query priority (or logical priority). If you want to give priority to a certain interrupt, you need to set IP and change the execution priority (or physical priority). It should be noted that after IP is set, when a low execution priority interrupt is running, if a high execution priority interrupt occurs, it will nest the call to enter the high execution priority interrupt. If you write a program in C language and use a register group when servicing an interrupt, please note that two interrupt service routines with different execution priorities should not use the same group of registers.

Look at the two questions, as follows:

1 When all interrupts are of low priority, if the overflow of timer 0 enters the interrupt, and during the interrupt processing, external interrupt 0 is also triggered, then does interrupt nesting occur?

2 If timer 0 is interrupted, the interrupt handler is entered. At this time, the trigger condition of external interrupt 1 is met. Because timer 0 has a higher priority than external interrupt 1, the interrupt handler of timer 0 continues to execute. Suppose during the execution of the timer interrupt handler, the trigger condition of external interrupt 1 disappears. Then after the interrupt of timer 0 is processed, will the program still enter the external interrupt 1 handler?

Answer 1: If the priority of external interrupt 0 is set by IP in advance, the CPU will stop the interrupt service of timer 0, enter the external interrupt 0 service routine, and then return to the timer 0 interrupt service routine after execution. Otherwise, it will not.

Answer 2: It will definitely enter the interruption; when the triggering condition of external interrupt 1 is met, the interrupt flag of external 1 will be set. Even if the triggering condition of external interrupt 1 disappears later, the set interrupt flag will not be cleared. Therefore, after the interrupt of timer 0 is processed, the program will still enter the external interrupt 1 handler after judging that the interrupt flag of the external interrupt is 1. Only when the reti instruction is executed in the external interrupt 1 handler will the hardware clear the interrupt flag of external interrupt 1 (this is why the interrupt return uses the reti instruction and cannot be replaced by ret)...