Collect

introduce

The SPI module implements duplex synchronous serial communication between the MCU and peripheral devices. Software can interact with the SPI module by polling flags or asynchronous interrupt notifications.

Abbreviations

abbreviation	Full name (English)	Full name (Chinese)
SPI	Serial Peripheral Interface	Serial Peripheral Interface
	Slave Select	Slave selection
SCK	Serial Clock	Serial Clock
MOSI	Master Output, Slave Input	Master (machine) (output) Slave (machine) (input)
MISO	Master Input, Slave Output	Master in, slave out
MOMI	Master Output, Master Input	Master in, master out
SISO	Slave Input, Slave Output	From in to out

characteristic

The SPI module includes the following features:

Can be set as master node or slave node
Selectable data width of 8 or 16 bits
Bidirectional mode
Slave selection signal output
Mode fault error flag with interrupt function
Double buffered data registers
Serial clock with programmable polarity and phase
Control SPI to operate in wait mode

Operation Mode

The SPI module can operate in three modes: run, wait, and stop.

Run mode
This is the basic running mode
Wait Mode
The SPI running in wait mode is a configurable low-power mode controlled by the SPISWAI bit in the SPICR2 register. In wait mode, if the SPISWAI bit is 0, the SPI will operate as in run mode. If the SPISWAI bit is 1, the SPI will enter a low-power state and the SPI clock generation will be turned off. If the SPI is configured as a master, any ongoing transfer will be stopped, but will resume after the CPU enters run mode. If the SPI is configured as a slave, data reception and transmission will continue so that the slave can keep pace with the master.
Stop mode
To save energy, the SPI is inactive in stop mode. If the SPI is configured as a master, any ongoing transfer will be stopped, but will resume after the CPU enters run mode. If the SPI is configured as a slave, data reception and transmission will continue so that the slave can keep pace with the master.

For details, refer to 4.7 “Low Power Mode Options”.

block diagram

The following figure gives an overview of the SPI architecture. The SPI module mainly consists of status, control and data registers, shift logic, baud rate generator, master/slave control logic and port control logic.

Figure 1. SPI block diagram

Pin Description

This section lists all the ports that may be connected to external chips. The SPI module has a total of 4 external pins.

MOSI — Master Out/Slave In pin

When configured as a master, this pin is used to transfer data out of the SPI module; when configured as a slave, it is used to receive data.

MISO — Master In/Slave Out pin

When configured as a slave, this pin is used to transfer data out of the SPI module; when configured as a master, it is used to receive data.

— Slave select pin

When configured as a master, this pin is used to output a select signal from the SPI module to the peripheral that is to receive data; when configured as a slave, it is used to receive a slave select signal.

SCK — Serial Clock pin

In master mode, this is the sync clock output pin; in slave mode, this is the sync clock receive pin.

Memory map and register definition

This section provides a detailed description of the address space and registers of the SPI module.

Module memory map

Figure 2 shows the memory map of the SPI module. The address listed before each register refers to the offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reading a reserved bit returns 0 and writing a reserved bit has no effect.

Figure 2. SPI register summary

Register Description

This section describes each register in address order. Each description contains a standard register diagram with associated numbers. This is followed by a description of the register bits and field functions, in bit order.

SPI Control Register 1 (SPICR1)

Figure 3. SPI Control Register 1

Read: anytime
Write: anytime

Table 2. SPICR1 field description

Fields	describe
7 SPIE	SPI Interrupt Enable Bit — If the SPIF or MODF status flag is set, this bit enables the SPI interrupt request. 0 Disable SPI interrupt. 1 Enable SPI interrupt
6 SPE	SPI System Enable Bit — This bit enables the SPI system and assigns the SPI port pins to the SPI system. If SPE is cleared, the SPI is disabled and forced into the idle state, and the status bits in the SPISR register are reset. 0 Disable SPI (low power). 1 Enable SPI, and the port pins are assigned to the SPI module.
5 SPTIE	SPI Transfer Interrupt Enable — If the SPTEF flag is set, this bit enables the SPI interrupt request. 0 Disable SPTEF interrupt. 1 Enable SPTEF interrupt
4 MSTR	SPI Master/Slave Mode Select Bit — This bit is used to select whether the SPI is a master or a slave. Switching the SPI from a master to a slave or vice versa will force the SPI system into an idle state. 0 SPI slave mode. 1 SPI master mode
3 CPOL	SPI Clock Polarity Bit — This bit is used to select whether the SPI clock is inverted. To transfer data between SPI modules, the SPI modules must use the same CPOL value. In master mode, changing this bit causes the ongoing transfer to be discarded and forces the SPI system to enter the idle state. 0 Use high active clock. SCK is low in the idle state. 1 Use low active clock. SCK is high in the idle state.
2 CPHA	SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, changing this bit causes ongoing transfers to be discarded and forces the SPI system into an idle state. 0 Data is sampled on odd-numbered edges. 1 Data is sampled on even-numbered edges.
1 SSOE	Slave Select Output Signal Enable — The SS output characteristics are dependent on this bit and the MODFEN bit, as described in Table 3. In master mode, changing this bit causes the transfer in progress to be discarded and forces the SPI system into the idle state.
0 LSBFE	Enable LSB-First — This bit does not affect the byte order within the data registers. The MSB is always placed first when reading or writing the data registers. In master mode, changing this bit causes the transfer in progress to be discarded and forces the SPI system into the idle state. 0 Most significant bit first. 1 Least significant bit first.

Table 3. Input/Output Selection

MODFEN	SSOE	Host Mode	Slave Mode
0	0	Not used by SPI	For input
0	1	Not used by SPI	For input
1	0	Input with MODF characteristics	For input
1	1	Is the slave select output	For input

SPI Control Register 2 (SPICR2)

Figure 4. SPI Control Register 2 (SPICR2)

Read: anytime
Write: anytime; writing to reserved bits has no effect.

Table 4. SPICR2 field description

Fields	describe
6 XFRW	Transfer Width — This bit is used to select the width of the transfer data. If 8-bit transfer width is selected, SPIDRL is a dedicated data register and SPIDRH is not used. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data register. Refer to 3.2.4 "SPI Status Register (SPISR)" for more information on the transfer/receive data processing and interrupt flag clearing mechanism. In master mode, changing this bit causes the transfer in progress to be discarded and forces the SPI system to enter the idle state. 0 8-bit transfer data width (n=8)1. 1 16-bit transfer data width (n=16)1.
4 MODFEN	Mode Fault Enable Bit — This bit enables MODF fault detection. If the SPI is in master mode and MODFEN is cleared, the pin is not controlled by the SPI module. In slave mode, the pin is an input regardless of the value of MODFEN. See Table 3 for a summary of the effects of MODFEN. In master mode, changing this bit causes a transfer in progress to be discarded and forces the SPI system into the idle state. 0 Port pin is not used by the SPI module. 1 Port pin with MODF feature .
3 BIDIROE	Output Enable in Single-Wire Bidirectional Mode — In single-wire bidirectional mode of operation (SPC0 = 1), this bit controls the MOSI and MISO output buffers. In master mode, this bit controls the output buffer of the MOSI port, and in slave mode, it controls the output buffer of the MISO port. In master mode, a change in SPC0 from 0 to 1 causes the transfer in progress to be discarded and forces the SPI system into the idle state. 0 Disables the output buffer. 1 Enables the output buffer.
1 SPISWAI	SPI module stop in wait mode — This bit is used to save power in wait mode . 0 SPI clock runs normally in wait mode. 1 Stop SPI clock generation in wait mode.
0 SPC0	Serial Pin Control Bit 0 — This bit is used to enable the single-wire bidirectional pin configuration as detailed in Table 5. In master mode, changing this bit causes the transfer in progress to be discarded and forces the SPI system into the idle state.

1. n is used as a placeholder for the selected transmission width.

Table 5. Single-wire bidirectional pin configuration

SPI Baud Rate Register (SPIBR)

Figure 5. SPI Baud Rate Register (SPIBR)

Read: anytime
Write: anytime; writing to a reserved bit has no effect.

Table 6. SPIBR field description

Fields	describe
6-4 SPPR[2:0]	SPI Baud Rate Preselect Bits — These bits determine the SPI baud rate as shown in Table 7. In master mode, changing this bit causes any transfers in progress to be discarded and forces the SPI system into the idle state.
2-0 SPR[2:0]	SPI Baud Rate Select Bits — These bits determine the SPI baud rate as shown in Table 7. In master mode, changing this bit causes any transfers in progress to be discarded and forces the SPI system into the idle state.

The baud rate division factor expression is as follows:

Then the baud rate is calculated as follows:

Notice:
Please refer to the SPI Electrical Specifications in the Electrical chapter of this data sheet for the minimum allowed baud rate.

Table 7. SPI baud rate selection example (25MHz bus clock)

SPI Status Register (SPISR)

SPI Status Register (SPI)
Figure 6. SPI Status Register (SPISR)

Read: Anytime
Write: No effect

Table 8. SPISR field description

Fields	describe
7 SPIF	SPIF Interrupt Flag — This bit is set after data has been transferred into the SPI data register. See Table 9 for how to clear the SPIF flag. 0 The transfer is not complete. 1 New data has been copied into the SPIDR.
5 SPTEF	SPI Transmitter Empty Interrupt Flag — If set, indicates that the data transmit register is empty. See Table 9 for how to clear this bit and place data into the data transmit register. 0 The SPI data register is not empty. 1 The SPI data register is empty.
4 MODF	Mode Fault Flag — When the SPI is configured as a master and the MODFEN bit in the SPICR2 register is set to enable mode fault detection, this bit is set if the SS pin is detected to be pulled low. For details, refer to the MODFEN bit description in 3.2.2 "SPI Control Register 2 (SPICR2)". This flag is automatically cleared by reading the SPI Status Register once (when MODF = 1) and then writing to the SPI Control Register 1. 0 No mode fault has occurred. 1 A mode fault has occurred.

Table 9. SPIF interrupt flag clearing sequence

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Keywords：MC9S12XEP100 Reference address：MC9S12XEP100 SPI module (S12SPIV5)

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