MC9S12XEP100 SPI module (S12SPIV5)

CPHA=0 transmission format

The first edge of the SCK line is used to latch the first data bit of the slave to the master and the first data bit of the master to the slave. For some peripherals, the first data bit of the slave data can be obtained from the slave data output pin as soon as the slave is selected. In this format, the first SCK edge needs to be  delayed by half a cycle after going low.

Half an SCK cycle later, a second edge appears on the SCK line. When this second edge appears, the value previously latched from the serial data input pin is shifted into the SPI shift register in the direction determined by the LSBFE bit.

After this second edge, the next bit of the SPI master data is transmitted to the serial output pin of the master, which is the serial input pin of the slave. This process is repeated 2n times the edge of the SCK line, with each odd edge latching the data and the even edge shifting the data.

Data reception is double buffered. During transmission, data is shifted serially into the SPI shift register; after the last bit is transmitted, the data is transferred into the parallel SPI data register.

After 2n SCK edges:

• The data that was previously in the master's SPI data register should now be in the slave's data register, and vice versa.

• The SPIF flag in the SPI status register is set, indicating that the transfer process has been completed.

Figure 12 is a timing diagram for SPI transfer when CPHA=0. The SCK waveform is also shown when CPOL=0 and 1. The diagram is both a timing diagram for the master and the slave because the SCK, MISO, and MOSI pins of the master and slave are directly connected together. The MISO signal line is the output of the slave, and the MOSI signal line is the output of the master. The master pin must be high or reconfigured as a general purpose output not related to SPI.

Figure 12. SPI clock format 0 (CPHA = 0), 8-bit data transfer width (XFRW = 0)

Figure 13. SPI clock format 0 (CPHA = 0), 16-bit data transfer width (XFRW = 1)

In slave mode, if   the line is not pulled high between successive transmissions, the previous data will not be transferred to the SPI data register, so only the last received data will be transferred. If  the line is pulled high for at least the minimum idle time (half SCK cycle) between successive transmissions, the data can be transferred to the SPI data register normally.

In master mode, as long as the slave select output is enabled,  the line is always pulled high for at least the minimum idle time between successive transactions.

CPHA=1 transmission format

Some peripherals require an SCK edge to make the first data bit valid on the data output pin, and then a second edge to latch the data into the system. In this format, the first SCK edge is initiated by setting the CPHA bit at the beginning of the n-cycle transfer.

The first SCK edge occurs immediately after a synchronization delay of half the SCK clock cycle. This first edge commands the slave to transmit its first data bit onto the master's serial data input pin.

Half an SCK period later, a second edge appears on the SCK pin. This is the latching edge for both the master and the slave.

When the third edge occurs, the value previously latched from the serial data input pin is shifted into the SPI shift register, and the shift direction depends on the LSBFE bit. After this edge, the master will output the next data bit of its data to the serial input pin of the slave.

This process will be repeated 2n times on the SCK line, with each even-numbered edge latching data and the odd-numbered edge shifting data.

Data reception is double buffered. During transmission, data is shifted serially into the SPI shift register; after the last bit is transmitted, the data is transferred into the parallel SPI data register.

After 2n SCK edges:

• The data that was previously in the master's SPI data register should now be in the slave's data register, and vice versa.

• The SPIF flag in SPISR is set, indicating that the transfer process has been completed.

Figure 14 shows the changes of the two clocks when CPHA=1. The diagram is both a timing diagram for the master and the slave, because the SCK, MISO, and MOSI pins of the master and slave are directly connected together. The MISO signal line is the output of the slave, and the MOSI signal line is the output of the master. It is the slave select input for the slave. The master's  pin must be high or reconfigured as a general purpose output not related to SPI.

Figure 14. SPI clock format 1 (CPHA = 1), 8-bit data transfer width (XFRW = 0)

Figure 15. SPI clock format 1 (CPHA = 1), 16-bit data transfer width (XFRW = 1)

The line can be held low (can be latched low) between successive transfers  . This format is sometimes preferred in systems where there is only one fixed master and one fixed slave driving the MISO data line.

• Back-to-back transfers in master mode
  In master mode, if a transfer is completed and new data is entered into the SPI data register, the data is sent out immediately without adding a minimum idle time.

The SPI interrupt request flag (SPIF) is consistent for both master and slave modes. SPIF will be set half a SCK period after the last SCK edge.

SPI baud rate generation

The baud rate generation includes a series of frequency division steps. The 6 bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1 and SPR0) determine the frequency division factor of the SPI module clock, which directly determines the baud rate of the SPI.

The SPI clock rate is determined by the values ​​of the baud rate preselect bits (SPPR2-SPPR0) and the baud rate select bits (SPR2-SPR0). The formula for the SPI module clock division factor is as follows:

For example: When all bits are 0 (default), the SPI module clock is directly divided by 2. When the selection bits (SPR2-SPR0) are 001 and the preselection bits (SPPR2-SPPR0) are 000, the module clock division factor becomes 4. When the selection bits are 010, the module clock division factor becomes 8.

For example, when the preselect bit is 001, the division factor determined by the select bit is multiplied by 2. When the preselect bit is 010, the division factor is multiplied by 3. Table 7 shows all the possibilities under a 25MHz bus clock. These two factors allow the clock to be divided by other powers of 2, such as division by 6, division by 10, etc.

The baud rate generator is activated only when the SPI is in master mode and a serial transfer is occurring. In other cases, the divider is disabled to reduce the IDD current.

• Notice:

• Refer to the SPI Electrical Specifications in the Electrical chapter of this data sheet for the minimum allowed baud rate.

Special Features

Output

 The output automatically drives the pin low during transmission to select the external device and drives it high when idle to deselect the external device. If used , connect the output pin to the input pin of the external device .

The output is only available when the SPI is operating normally in master mode by setting the SSOE and MODFEN bits as described in Table 3.

When the output is enabled , the mode fault feature is disabled.

• Notice:

• Be careful when using the output feature in a multi-master system  because the mode fault feature cannot be used to detect systematic errors between masters.

Single-wire bidirectional mode (MOMI or SISO)

The single-wire bidirectional mode is selected when the SPC0 bit in the SPI Control Register 2 is set (see Table 11). In this mode, the SPI uses only one serial data pin to connect to the external device. The MSTR bit determines which pin is used. For master mode, the MOSI pin becomes the serial data I/O (MOMI) pin; for slave mode, the MISO pin becomes the serial data I/O (SISO) pin. The SPI system does not use the MISO pin in master mode and does not use the MOSI pin in slave mode.

Table 11. Normal mode and single-line bidirectional mode

The direction of each serial I/O pin is determined by the BIDIROE bit. If the pin is configured as an output, the serial data from the shift register drives the pin. This pin is also the serial input of the shift register.

• SCK is an output in master mode and an input in slave mode.

• It is either an output or an input in master mode, but is always an input in slave mode.

• The single-wire bidirectional mode does not affect the functionality of SCK and .

• Notice:

• In single-wire bidirectional master mode, when mode fault is enabled, both MISO and MOSI pins may be used by the SPI, although in this mode MOSI is usually used for transmission without MISO. If a mode fault occurs, the SPI automatically switches to slave mode. In this way, MISO is used by the SPI and MOSI is not used. Be sure to take this into account if the MISO pin is used for other purposes.

Error Conditions

SPI has one error condition:

• Mode Failure Error

Mode Failure Error

When the SPI is configured as a master, if the input pin is pulled low, it indicates that a system error has occurred and more than one master wants to drive the MOSI and SCK lines at the same time. Under normal circumstances, this is not allowed to happen. If the MODFEN bit is 1, the MODF bit in the SPI status register will be automatically set.

In the special case that the SPI is in master mode and the MODFEN bit is 0,  the pin is not used by the SPI. In this special case, the mode fault function is disabled and MODF remains 0. In the case that the SPI system is a slave, the pin is a dedicated input pin. A mode fault error will not occur in slave mode.

If a mode fault error occurs, the SPI switches to slave mode unless the slave output buffer is disabled. This forces the SCK, MISO, and MOSI pins to high impedance inputs to avoid conflict with another output device. Transfers in progress are discarded and the SPI is forced into an idle state.

If a mode fault error occurs in the single-wire bidirectional mode when the SPI system is configured in master mode, the output enable of MOMI (MOSI in the single-wire bidirectional mode) will be cleared if it is 1. A mode fault error will not occur in the single-wire bidirectional mode when the SPI system is configured in slave mode.