ARM processor and ARM processor working mode

Introduction: ARM microprocessors generally have two working states and can switch between the two states:
the first is the ARM state, in which the processor executes 32-bit word-aligned ARM instructions;
the second is the Thumb state, in which the processor executes 16-bit, half-word-aligned Thumb instructions.

ARM processor status

ARM microprocessors generally have two working states and can switch between the two states:

The first is the ARM state, in which the processor executes 32-bit word-aligned ARM instructions;

The second is the Thumb state, in which the processor executes 16-bit, half-word aligned Thumb instructions.

During the execution of the program, the microprocessor can switch between the two working states at any time, and the change of the processor working state does not affect the processor's working mode and the contents of the corresponding registers. However, the ARM microprocessor should be in the ARM state when it starts executing the code.

ARM Processor Modes

ARM microprocessor supports 7 operating modes, namely:

User mode (usr): The normal program execution state of the ARM processor.

Fast interrupt mode (fiq): used for high-speed data transmission or channel processing.

External interrupt mode (irq): used for general interrupt processing.

Supervisor mode (svc): The protection mode used by the operating system.

Data access termination mode (abt): This mode is entered when data or instruction prefetching is terminated and can be used for virtual storage and storage protection.

System mode (sys): runs privileged operating system tasks.

Defined instruction abort mode (und): This mode is entered when an undefined instruction is executed and can be used to support software emulation of hardware coprocessors.

ARM Registers

The ARM processor has a total of 37 registers, including: 31 general registers, including the program counter (PC). These registers are all 32-bit registers. And 6 32-bit status registers.

I won't go into detail about registers here, but those who are interested can search the Internet for a lot of information on this topic.

Exception handling

When the normal program execution flow is temporarily stopped, it is called an exception, such as processing an external interrupt request. Before processing the exception, the current processor state must be retained so that when the exception is processed, the current program can continue to execute. The processor allows multiple exceptions to occur at the same time, and they will be processed according to a fixed priority. When an exception occurs, the ARM microprocessor will perform the following steps:

The basic steps to enter exception handling:

Store the address of the next instruction in the corresponding link register LR so that the program can resume execution from the correct location when handling an exception. Copy the CPSR to the corresponding SPSR. Force the operating mode bit of the CPSR to be set according to the exception type.

Force the PC to fetch the next instruction from the relevant exception vector address and jump to the corresponding exception handler. If the processor is in Thumb state when the exception occurs, the processor automatically switches to ARM state when the exception vector address is loaded into the PC.

The ARM microprocessor's response to an exception can be described in pseudo code as follows:

R14_ = Return Link

SPSR_= CPSR

CPSR[4:0] = Exception Mode Number

CPSR[5] = 0; when running in ARM working state

If == Reset or FIQ then; when responding to a FIQ exception, new FIQ exceptions are prohibited

CPSR[6] = 1

PSR[7] = 1

PC = Exception Vector Address

After the exception is handled, the ARM microprocessor will perform the following steps to return from the exception:

Subtract the corresponding offset from the value of the link register LR and send it to the PC.

Copy the SPSR back into the CPSR.

If the interrupt disable bit is set when entering exception processing, it must be cleared here.