ARM architecture analysis

　　I. Introduction

　　With the rapid development of various consumer products such as smart phones, tablet computers, and car electronics in the past two years, ARM architecture processors, as the processing core of these consumer products, have also made great progress, even defeating Intel and taking the lead in the mobile embedded field. This article will first introduce the development history of ARM architecture, and then focus on the architecture of its most advanced Cortex series processors, as well as the support of these structures for various software platforms such as JAVA and .NET.

　　2. The history of ARM architecture and its new developments

　　2.1 Market Prospects of ARM Architecture

　　Although ARM (Acorn RISC Machine) from the UK is famous for its ARM processor, its unique business model determines that ARM itself does not produce processors. This is very different from Intel, which is vertically integrated from R&D to production to shipment. ARM adopts a licensing and commission business model (Intellectual Property Core, abbreviated as IP-Core): the company develops its own processor architecture, and then licenses the intellectual property rights of this architecture to processor manufacturers such as Qualcomm, Samsung and other semiconductor manufacturers for a fee. These manufacturers only need to pay a low commission to ARM for each chip using the ARM architecture. Due to this innovative business model and low cost, coupled with the low power consumption characteristics of the ARM system, the ARM system has become more powerful in the 32-bit embedded electronic consumer product market that is sensitive to price and battery life, and basically occupies 100% of the market share of 32-bit embedded consumer flat. Today, ARM chips are even capable of competing with Intel's ATOM processors in netbooks and tablets that require higher computing speeds. The recently popular Apple iPad uses a processor architecture deeply customized by ARM, and many other tablets and smartphones running Android systems also use ARM architecture processing cores. This shows the unparalleled advantages of ARM architecture in the mobile consumer electronics market.

　　2.2 ARM system development history

　　1985——The first ARM chip, ARM1 Sample version, was born.

　　1986 - ARM2, a processor with a 32-bit data bus, a 26-bit address bus, and 16 32-bit registers, was put into mass production.

　　Late 1980s - Apple Computer begins working with Acorn to develop a new version of the ARM core.

　　1991 - Collaboration with Apple resulted in the creation of ARM6, which was used in Apple's Apple Newton PDA and Acorn Risc-PC as their processors. In that year, ARM was formally established as a subsidiary of Acorn.

　　From 1991 to date, ARM's products have spanned various computing fields such as application processors, embedded processors, expert systems, and have become the preferred processor architecture for the mobile consumer electronics market and complex industrial control applications.

　　2.3 Introduction to ARM Product Series

　　2.3.1 Classic ARM processor

　　The processor architectures included in this series are:

　　l ARM11 series——High-performance processors based on ARMv6 architecture

　　l ARM9 series - commonly used processors based on ARMv5 architecture

　　l ARM7 series——classic processors for general applications

　　This series is suitable for those who want stable products in new applications. These processors offer many features, excellent power efficiency and a wide range of operating capabilities for cost-sensitive solutions. Billions of these processors are shipped each year, ensuring that designers have access to the widest range of systems and resources, thereby minimizing integration issues and shortening time to market.

　　2.3.2 ARM Cortex Embedded Processor

　　This series of processor architectures are:

　　l Cortex-R series——Excellent performance for real-time applications

　　l Cortex-M series - cost-sensitive solution for deterministic microcontroller applications

　　The Cortex-M series processors were developed primarily for the microcontroller space, where fast and highly deterministic interrupt management is required while keeping gate count and possible power consumption to a minimum; the Cortex-R series processors were developed for deeply embedded real-time applications, balancing the needs of low power consumption, good interrupt behavior, excellent performance and high compatibility with existing platforms.

　　2.3.3 ARM Cortex Application Processor

　　This series includes processor architectures only

　　l Cortex-A series - high-performance processors with open operating systems

　　Cortex-A can achieve a clock speed of up to 2GHZ+ in advanced process nodes. Due to such excellent performance, this processor architecture can be used in the next generation of Internet devices. The series provides single-core and multi-core types, four options of NEON multimedia processing modules and advanced floating-point execution units and processing units.

　　2.3.4 ARM Expert Processor

　　This series includes processor architectures only

　　l SecurCore - processor for high-security applications

　　l FPGA core - processor for FPGA

　　This series of processors is mainly designed to meet the demanding needs of some specific markets. SecurCore can be used for mobile phone SIM cards and other identification applications, integrating a variety of technologies that can provide users with excellent performance and detect and avoid security attacks.

　　2.4 ARM Instruction Set

　　When talking about the ARM instruction system, we must first make it clear that the ARM architecture is different from the x86. It is a RISC (Reduced Instrument Set Computer) architecture. Therefore, in the ARM instruction system, the instructions are relatively more regular, symmetrical, and simple. Moreover, there are less than 100 instructions, there are only 2 to 3 basic addressing modes, and the instruction word length is relatively consistent, and all are completed within a single clock cycle to facilitate pipeline operation. In ARM7, a three-level pipeline is used: value acquisition, decoding, and execution. ARM9 and ARM10 use five-level and six-level pipelines. ARM memory access uses the LOAD-STORE structure, which can average the execution time of each instruction, which is conducive to the implementation of efficient pipelines. The use of this structure also means that instructions must be operated between registers, so there are a large number of registers (no less than 32) in the ARM system.

　　2.4.1 ARM instructions and Thumb instructions

　　The ARM instruction set can be either 32-bit ARM instructions or 16-bit Thumb instructions, which is mainly for compatibility with application systems with 16-bit data buses. All Thumb instructions have corresponding ARM instructions. Thumb is just a true subset of ARM, and Thumb instructions have abandoned some features of the ARM instruction set, such as most Thumb instructions are executed unconditionally, while almost all ARM instructions are executed conditionally. For example, most Thumb instructions have a limited length, and the destination register is one of the source registers, which is similar to the x86 assembly instruction set.

　　The advantage of Thumb instruction is that it can save a lot of system storage space while retaining the advantages of 32-bit code, because the operands in the Thumb instruction set are still 32 bits, and the instruction address is also 32 bits, but the instruction encoding becomes 16 bits, while the ARM instruction is 32 bits. Therefore, in comparison, to achieve the same function, the number of Thumb instructions is slightly more than ARM. Figure 2.1 is a comparison of the instructions of "Add Rd, #Constant" in Thumb state and ARM state:

　　From the above figure, we can clearly see the simplification of Thumb instructions. Therefore, the storage space of Thumb is only 60%~70% of the storage space of ARM, but the number of Thumb instructions is 30%~50% more than that of ARM instructions. If 32-bit memory is used, ARM instructions will be about 40% faster than Thumb instructions due to the small number of instructions, while when 16-bit memory is used, Thumb instructions will be 40%~50% faster. At the same time, compared with ARM, the power consumption of Thumb instructions will be reduced by about 30%. However, Thumb instructions also have their limitations. First, the offset range. In Thumb instructions, the conditional transfer offset is only 8 bits, which means that it can only be conditionally transferred within the range of 256Byte. In unconditional transfer, there can be a 16-bit offset, which is 32 bits in ARM instructions, which greatly improves flexibility. At the same time, multiplication and accumulation are not supported in Thumb instructions, there are no coprocessor instructions, no semaphore instructions, and no CPSR instructions.

　　When faced with the trade-off between the two, as in countless other cases, the best solution is to give full play to the strengths of each. If the system has higher performance requirements, 32-bit memory and ARM instruction set should be used, while if power consumption and cost requirements are higher, Thumb instruction set should be used. However, if the two are used in combination to give full play to their respective advantages, better results will be achieved.

　　The basic format of ARM instructions is as follows:

　　《opcode》 {《cond》} {S} 《Rd》 , 《Rn》{, 《operand2》}

　　Among them, the items in "" are required, and the items in {} are optional. opcode is the instruction mnemonic; cond is the execution condition of the action; S indicates the impact on the value of the CPSR register (program status register). If not added, it means that the value of CPSR is not affected; Rd indicates the target register of the operation result; Rn indicates the register of the first operand; operand2 indicates the second operand, which is optional.

　　At the same time, ARM chips also support coprocessors. The ARM instruction set contains corresponding instructions for data operations, data reading, data writing, and register transfer between the CPU and the coprocessor.