Introduction to ARM processor and RISC characteristics

Introduction to the first ARM processor and RISC characteristics

Introduction to ARM Processor

ARM (Advanced RISC Machines) is a 32-bit RISC (reduced instruction set) processor architecture, and the ARM processor is a microprocessor under the ARM architecture. ARM processors are widely used in many embedded systems. The characteristics of ARM processors include fixed instruction length, high execution efficiency, and low cost.

Main features of RISC design

1. Instruction set - RISC reduces the types of instruction sets, usually one instruction per cycle, using a fixed-length instruction format, and the compiler or programmer completes a complex operation through several instructions. The instruction length of the CISC instruction set is usually not fixed.

2. Pipeline - RISC uses single-cycle instructions with fixed instruction length, which facilitates pipeline operation execution.

3. Registers - RISC processors have more general registers and more register operations. For example, the ARM processor has 37 registers.

4. Load/Store structure - use load/store instructions to read and write data from memory in batches to improve data transmission efficiency.

5. The addressing method is simplified, the instruction length is fixed, and the instruction format and addressing mode types are reduced.

Second ARM instruction set features

ARM processors are based on RISC, but not pure RISC architecture. In order to make ARM processors better meet the needs of embedded systems, the ARM instruction set is different from the pure RISC instruction set in the following aspects:

1. The number of cycles of some specific instructions is variable. For example, the execution cycle of Load/Store instructions for loading or storing multiple registers is uncertain, which depends on the number of related registers. If continuous memory addresses are accessed, performance can be improved because continuous memory access is faster than random access. Based on this feature, since there are usually multiple registers and memory data exchange operations at the beginning and end of the function, the number of instructions for the corresponding operation will be reduced, which improves the density of the code.

2. The built-in barrel shifter generates more complex instructions. The barrel shifter is a hardware component that processes the data in a register before it is used by an instruction. The barrel shifter extends the functionality of many instructions, thereby improving the performance of the core and increasing code density.

3. Thumb 16-bit instruction set. The ARM processor has two working states, one is ARM state and the other is Thumb state. The instruction length in ARM state is 32 bits, and the instruction length in Thumb state is 16 bits. This feature enables ARM to execute both 16-bit instructions and 32-bit instructions, thereby enhancing the functions of the ARM core.

4. Conditional execution. Instructions are executed only when a certain condition is met. This feature can reduce the number of branch instructions, thereby improving performance and increasing code density.

5. Enhanced instructions. Some powerful digital signal processor ( DSP ) instructions are added to the standard ARM instructions to support fast 16*16 multiplication operations and saturation operations. These enhanced instructions of ARM make it possible to implement ARM processors without adding DSP.

Third ARM processor features

1. ARM instructions are all 32-bit fixed-length

2. Rich number of registers (37 registers)

3. Ordinary Load/Store Instructions

4. Load/Store instructions for multiple registers

5. Conditional execution of instructions

6. A single instruction in a single clock cycle completes data shift operations and ALU operations

7. Extending the functionality of ARM processors through variants and coprocessors

8. Expanded 16-bit Thumb instructions to improve code density

Fourth ARM processor naming rules 

ARM programming model 

1. Word: In the ARM architecture, the length of a word is 32 bits.

2. Half-Word: In the ARM architecture, the length of a half-word is 16 bits.

3. Byte: In the ARM architecture, the length of a byte is 8 bits.

ARM processor storage format

The ARM architecture treats memory as a linear combination of bytes starting at address 0. As a 32-bit microprocessor, the maximum addressing space supported by the ARM architecture is 4GB.

The ARM architecture can store word data in two ways, big-endian mode and little-endian mode.

Big-endian mode (high-low-high): The high byte of the word is stored in the low-address byte unit, and the low byte of the word is stored in the high-address byte unit.

Little-endian mode (high-high-low-low): The high byte of the word is stored in the high-address byte unit, and the low byte of the word is stored in the low-address byte unit.

ARM processor working status

From a programming perspective, ARM microprocessors generally have two working states: ARM and Thumb, and can switch between the two states.

1. ARM state: At this time, the processor executes 32-bit word-aligned ARM instructions, and most of the work is in this state.

2. Thumb state: At this time, the processor executes 16-bit half-word aligned Thumb instructions.

ARM processor working mode

1. User mode (usr, User Mode): The normal program execution state of the ARM processor.

2. Fast Interrupt Request Mode (fiq): used for high-speed data transmission or channel processing. This mode is entered when a fast interrupt is triggered.

3. External interrupt mode (irq, Interrupt Request Mode): used for general interrupt processing. This mode is entered when an external interrupt is triggered.

4. Supervisor Mode (svc): The protection mode used by the operating system. It is entered when the system is reset or the software interrupt instruction SWI is executed.

5. Data access abort mode (abt, Abort Mode): This mode is entered when data or instruction prefetching is aborted and can be used for virtual storage and storage protection.

6. System Mode (sys): Runs privileged operating system tasks.

7. Undefined instruction abort mode (und, Undefined Mode): This mode is entered when an undefined instruction is executed and can be used to support software emulation of hardware coprocessors.

Except for the user mode, the other six modes are privileged modes. Except for the user mode and system mode, the other five modes are exception modes.

In privileged mode, programs can access all system resources. The difference between non-privileged mode and privileged mode is that some operations are only allowed in privileged mode, such as directly changing modes and enabling interrupts. In order to ensure data security, MMU generally divides the address space, and only privileged mode can access all address spaces. If user mode needs to access hardware, it must switch to privileged mode to allow access to hardware.

ARM processor register organization

ARM has a total of 37 32-bit registers, 31 of which are general registers and 6 are status registers, including R0-R15, R8_fiq-R14_fiq, R13_svc, R14_svc, R13_abt, R14_abt, R13_irq, R14_irq, R13_und, R14_und, CPSR, SPSR_fiq, SPSR_svc, SPSR_abt, SPSR_irq, SPSR_und. As shown in the figure.

General registers include R0-R15, which can be divided into 3 categories:

1. Ungrouped registers R0-R7

In all operating modes, ungrouped registers point to the same physical registers, and they are not used for special purposes by the system. Therefore, when interrupt or exception processing performs exception mode conversion, since different processor operating modes use the same physical registers, data in the registers may be destroyed.

2. Group registers R8-R14

For grouped registers, the physical registers they access each time are related to the current processor operation mode, as shown in the figure above.

R13 is often used to store the stack pointer. Users can also use other registers to store the stack pointer, but in the Thumb instruction set, some instructions require the use of R13 to store the stack pointer.

R14 is called the link register (LR). When a subroutine is executed, R14 can get a backup of R15 (PC). After the subroutine is executed, the value of R14 is copied back to PC, that is, R14 is used to save the return address.

3. Program Counter PC (R15)

Register R15 is used as the program counter (PC). In ARM state, bits [1:0] are 0 and bits [31:2] are used to save the PC. In Thumb state, bit [0] is 0 and bits [31:1] are used to save the PC.

Since the ARM architecture uses multi-stage pipeline technology, for the ARM instruction set, PC always points to the addresses of the next two instructions of the current instruction, that is, the value of PC is the address value of the current instruction plus 8 bytes.

Program Status Registers CPSR and SPSR

CPSR (Current Program Status Register), CPSR can be accessed in any operating mode. It includes condition flags, interrupt disable bits, current processor mode flags, and other related control and status bits.

Each operating mode has a dedicated physical status register called SPSR (Saved Program Status Register). When an exception occurs, SPSR is used to save the current value of CPSR. When exiting from the exception, SPSR can restore CPSR.

Since user mode and system mode are not exception modes, there is no SPSR in these two states. Therefore, the result of accessing SPSR in these two states is unknown.

The structure of CPSR data storage:

1.N (Negative): When performing operations on signed numbers represented by two's complement, N=1 indicates that the result is negative, and N=0 indicates that the result is positive or zero.

2.Z (Zero): Z=1 means the result of the operation is 0, and Z=0 means the result of the operation is non-zero.

3.C (Carry): There are 4 ways to set the value of C:

(1) Addition instructions (including comparison instructions CMP)

(2) When the operation generates a carry (unsigned number overflow), C = 1, otherwise C = 0

(3) Subtraction operation (including comparison instruction CMP)

(4) When the operation results in a borrow (unsigned overflow), C = 0, otherwise C = 1