ARM commands LDREX and STREX implement spinlock

There is this section under include/asm-arm/spinlock.h

#if __LINUX_ARM_ARCH__ < 6
#error SMP not supported on pre-ARMv6 CPUs
#endif

Okay, the premise is: only ARM core version >= 6 can continue:

All spin lock primitives end up using the following basic type: 

static inline void __raw_spin_lock(raw_spinlock_t *lock)
{
    unsigned long tmp;

1 __asm__ __volatile__(
2"1: ldrex %0, [%1]n"
3" teq %0, #0n"
4" strexeq %0, %2, [%1]n"
5" teqeq %0, #0n"
6" bne 1b"
7 : "=&r" (tmp)
8 : "r" (&lock->lock), "r" (1)
9 : " cc");

    smp_mb();
}

[Key Points of Instruction]:

The ldrex instruction is only available after core 6. It is paired with strex. You can ask the bus to monitor whether there are other CPUs or DMAs between ldrex and strex to access this address. If so, strex will The value in the first register is set to 1 (non-exclusive by this CPU) and the store action fails. If not, strex will set the value in the first register to 0 (exclusive access by this CPU) and the store action is made. success.

Code Trace Discussion: 

Line 1: __volatile__ tells the compiler not to perform optimization actions on this assembly template, because we have a loop to read the memory. The optimization results may cause the compiler to use a register to cache its value, which will not be honest. Really read the memory... Haha, this is not the action we want!

Line 2: Read the lock into tmp and ask the bus monitor for this memory

Line 3: Test whether the lock is 0. If it is not 0, it means that the lock has been obtained by someone else, then Line 4 and 5 will not be executed, and then Line 6 will branch and perform the spin action. If it is 0, it means there is a chance to obtain the lock and continue to Line 4.5. 

Line 4: Here comes the point! , check the results of the bus monitor. If it is exclusive access, tmp is set to 0 and 1 is stored in the lock. If it is non-exclusive access (other CPU has touched it), tmp is set to 1 and no action is taken to store the lock.

Line 5: Test tmp

Line 6: If tmp is 0, it means that the lock action just performed is exclusive and you can leave the loop. If tmp is 1, the spin action is performed.

Line 7: tmp uses register to operate, both input and output, let it be %0

Line 8: &lock->lock uses register to operate, let it be %1, value 1 uses register to operate, let it be %2

Line 9: This template will be changed to condition code and added to the clobber list to tell the compiler that this is the case

Well, I finally finished reading it. I really admire those coding kernel hackers....

Questions to think about: Before ARM v6, there was a SWP instruction that could lock bus and swap memory. It could also be used to complete exclusive access. But compared with ldrex and strex, what are the disadvantages of this pair of instructions?

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