15. Detailed explanation of I2C communication for ARM bare metal learning

Commonly used serial bus protocols:

The commonly used serial buses for data transmission between microcomputers and peripherals are I2C bus, SPI bus and SCI bus.

The I2C bus communicates in a synchronous serial 2-wire manner (one clock line and one data line).

The SPI bus communicates in a synchronous serial 3-wire manner (a clock line, a data input line, and a data output line).

The SCI bus communicates in an asynchronous manner (one data input line and one data output line).

1-wire, that is, single-wire bus, is also called single bus. For example, the DS18B20 temperature sensor uses this bus structure.

Here we focus on explaining the I2C serial bus in detail. We will take the IIC timing diagram in the data sheet as an example. Friends who cannot understand the timing diagram must make up for it.

1. Composition and working principle of I2C serial bus.

1.I2C bus is a serial bus launched by PHLIPS, which has only two bidirectional signal lines, one is the data line SDA (serial data I/O), and the other is the clock line SCL (serial clock).

2. As shown in the figure below, multiple devices can be connected to one IIC bus, and each device has a unique address, so it can be marked

The data communication adopts the master-slave mode, where the host is responsible for actively contacting the slave, and the slave passively responds to the data and responds in time.

2.I2C bus transmission protocol

1. Data bit validity regulations:

When SCL is at a high level, the data on the data line must remain stable, and the SDA state is allowed to change only when the SCL signal is at a low level.

2.I2C start and end signals

When the SCL line is at a high level, the change of the SDA line from a high level to a low level indicates a start signal;

When the SCL line is at a high level, the change of the SDA line from a low level to a high level indicates a termination signal;

Response signal (ACK): After receiving 8 bits of data, the receiver pulls down the SDA level in the 9th clock cycle. That is, after receiving 8 bits of data, the IC that receives data sends a specific low-level pulse to the IC that sends data, indicating that the data has been received. After the CPU sends a signal to the controlled unit, it waits for the controlled unit to send a response signal. After receiving the response signal, the CPU determines whether to continue to transmit the signal based on the actual situation. If no response signal is received, it is determined that the controlled unit has a fault; as shown in the figure

There will be no ACK signal in the following three situations:

A. When the slave cannot respond to the slave address (the slave is busy with other things and cannot respond to the IIC bus operation or this address does not correspond to the slave), the SDA line is not pulled low in the 9th SCL cycle, that is, there is no ACK signal. At this time, the host sends a P signal to terminate the transmission or resends an S signal to start a new transmission

B. When the slave receiver cannot receive more data during the transmission process, it will not send an ACK signal. The host realizes this and sends a P signal to terminate the transmission or sends an S signal to start a new transmission.

C. The host receiver will not send an ACK signal when receiving the last byte, so the slave transmitter releases the SDA line, allowing the host to send a P signal to end the transmission.

3.I2C byte transmission and response

Each byte must be 8 bits long. When transmitting data, the highest bit (MSB) is transmitted first, and each transmitted byte must be followed by an acknowledge bit (i.e., a frame has 9 bits in total). As shown in the figure

4. The role of the response bit

When the host sends data, each time it sends a byte of data, it needs to read the slave's response bit. When the slave is idle and can receive the byte of data, the slave will send a response (the 9th bit of a frame of data is "0"). When the slave is busy with other work and has no time to receive the data sent by the host, the slave will send a non-response (the 9th bit of a frame of data is "1"). The host should send a termination signal to end the continued transmission of data. The host determines whether the slave has successfully received the data through the response bit sent by the slave.

When the master receives data, it must send a signal to the slave to end the transmission after receiving the last data byte. This signal is implemented by a "non-acknowledge" to the slave. Then, the slave releases the SDA line to allow the master to generate a termination signal.

Here is a signal timing diagram of the IIC bus during data transmission. If you study the timing diagram carefully, everything can be easily solved.

● How does I2C communicate?

How does S5PV210 distinguish multiple slave devices when sending or receiving data? See the figure below: After starting communication, the master device first sends a 7-bit slave device address and a 1-bit read or write command.

(1) If it is a write command, the master device frees the SDA communication line (If the I2C-bus is free, both SDA and SCL lines should be both at High level. Samsung user manual), that is, SDA

The slave device then ACKs the master device (pulls down SDA) to indicate that the command has been received (S). The master device then sends 8-bit data, and the slave device ACKs (A). Then it ends (P).

(2) If it is a read command, the slave device first ACKs the master device (pulls SDA low), then sends 8 bits of data. The master device ACKs the slave device (pulls SDA low), and the slave device continues to send until the master device stops receiving.

As shown in the figure below, the white bits are sent by the master device, and the gray bits are sent by the slave device.

3. I2C controller of S5PV210

The function of IIC controller:

The communication timing is generated by the hardware controller, and the software only needs to control the configuration of the register of the corresponding IIC controller. The timing of the two communicating parties will be allocated by the controller itself.

1. Structural block diagram analysis

Clock source: PCLK_PSYS = 65MHz, after internal frequency division, the CLK of the I2C controller is finally obtained. During communication, this CLK will be transmitted to the slave device through the SCL line.

Bus control logic unit: generates IIC communication timing (sets I2CCON, I2CSTAT)

Shift register: converts the byte data to be sent into 1 bit and shifts it to the SDA line

I2CCON: Clock Configuration

I2CSTAT: Operation mode and condition bit transmission, used together with I2CCON to generate communication timing and IIC interface configuration

I2CADD: IIC address, used to write your own address

I2CDS: Data shifter, the send and receive addresses are placed here

Comparator + address register: When used as a slave device, the received address is compared with the address register address.

2. Analyze the I2C clock

(1) The I2C clock source comes from PCLK (PCLK_PSYS, equal to 65MHz), which is obtained after 2-level frequency division.

(2) The first level of frequency division is bit 6 of I2CCON, which can obtain an intermediate clock I2CCLK (equal to PCLK/16 or PCLK/512)

(3) The second level of frequency division is to obtain the final I2C controller working clock, which is based on the intermediate clock I2CCLK. The frequency division factor is [1,16]

(4) The final clock is a 2-level divided clock, for example, set it like this: 65000KHz/512/4 = 31KHz

3. Main registers I2CCON, I2CSTAT

I2CCON + I2CSTAT: Mainly used to generate communication timing and I2C interface configuration, and analyze the bit positions of the two registers

I2CCON Register:

I2CSTAT Register:

4. Analysis of the communication process of the I2C controller of S5PV210

(1) Flowchart of the master transmission mode of S5PV210

(2) Flowchart of the master receiving mode of S5PV210

In the I2C communication code in the SoC, we only need to follow the sequence of the flowchart in the figure above to complete the communication. The internal circuit module of the I2C controller has helped us realize the communication timing, and we do not need to care about the specific timing process.

5. I2C sensor on S5PV210 board

● The device address of the I2C slave device

(1) The I2C address of KXTE9 is fixed to 0b0001111 (0x0f)

(2) The I2C slave device address itself is 7 bits, but when sending the I2C slave device address in I2C communication, 8 bits are actually sent. The high 7 bits (bit7-bit1) of these 8 bits correspond to the 7-bit address of the I2C slave device, and the lowest bit (LSB) stores the R/W information (that is, whether the next data is written by the master device and read by the slave device (corresponding to 0), or read by the master device and write by the slave device (corresponding to 1))

(3) Based on the above, for KXTE9,

When the master device (SoC) writes information to gsensor, SAD should be: 0b00011110 (0x1E)

If the master device reads the gsensor information, SAD should be: 0b00011111 (0x1F)**

● IIC sensor read and write register flow chart

6. Analysis of SoCI2C controller communication code

7. I2C sensor communication code analysis

Currently, we can only analyze the usage of corresponding registers based on the code, and we don't understand the internal driver code.

The drive backfill