The GS waveform oscillation of MOSFET can be eliminated in this way!

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The GS waveform oscillation of MOSFET can be eliminated in this way! [Copy link]

For us power engineers, we often look at waveforms, such as input waveform, MOS switch waveform, current waveform, output diode waveform, chip waveform, and GS waveform of MOS tube. Let's take the switch GS waveform as an example to talk about the GS waveform.

When we test the GS waveform of the MOS tube, we sometimes see a waveform like the one in the figure below. It is a very good square wave output at the output end of the chip, but once it reaches the G pole of the MOS tube, there will be problems and oscillation. When the oscillation is small, it can still pass, but sometimes the oscillation is very large, and it makes people worry about whether it will restart.

What is the oscillation in this waveform? Is there any way to eliminate it?

Let’s take a look

The waveform coming out of IC is normal, but the waveform at both ends of C1 oscillates. In fact, this oscillation is caused by the series oscillation of three components: R1, L1 and C1. R1 is the driving resistor, which is added by us. L1 is the parasitic inductance of the wiring on the PCB. C1 is the parasitic capacitance of the MOS tube GS.

For an RLC series resonant circuit, L1 and C1 do not consume power, and resistor R1 plays a damping role in resistance oscillation.

In fact, the value of this resistor determines whether or not there will be oscillation across C1.

1. When R1>2(L1/C1)^0.5, S1 and S2 are unequal real roots. Overdamping condition.

In this case, there is basically no oscillation.

2. When R1=2(L1/C1)^0.5, S1 and S2 are two equal real roots. Critical case.

In this case, any oscillations are relatively weak.

3. When R1<2(L1/C1)^0.5, S1 and S2 are conjugate complex roots. Underdamped condition.

In this case, the circuit is bound to oscillate.

So if the above oscillations need to be eliminated, we have several options.

1. Increase the resistance R1 so that R1 ≥ 2 (L1 / C1) ^ 0.5 to eliminate oscillation. Increasing R1 will reduce the power efficiency, so we generally choose a resistance value close to the critical value.

2. Reduce the parasitic inductance of PCB traces. This means that you must pay attention to it during layout and wiring.

3. Increase C1. It is often difficult for us to change this. Increasing C1 will greatly increase the opening time, so we generally do not change it.

Therefore, the most important thing is to pay special attention to the length of the trace when laying out the wiring. The shorter the better. In addition, R1 can be appropriately increased.

伟林电源

The author seems to be familiar with the application of MOS? Do you work as a FAE?