Bit 0 CEN: Enable counter
0: disable the counter;
1: Enable the counter.
Note: After the software sets the CEN bit, the external clock, gate mode and encoder mode can work. However, the trigger mode can
The CEN bit is automatically set by hardware.
(6) TIMX_PSCR prescaler register
Bit 7:0 PSC[15:7]: The upper 8 bits of the prescaler value
PSC[7:0]: The lower 8 bits of the prescaler
The prescaler is used to divide the frequency of CK_PSC.
The counter clock frequency (fCK_CNT) is equal to fCK_PSC/(PSCR[15:0]+1).
PSCR contains the value that is currently loaded into the prescaler register when an update event occurs (an update event includes a counter being
The UG bit of TIM_EGR is cleared to 0 or is cleared to 0 by the slave controller operating in reset mode). This means that an update event must be generated in order for the new value to take effect.
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