The AVR manual says:
"The TXC flag can be used to check whether the transmission of a data frame has been completed, and the RXC flag can be used to check whether there is any data in the receive buffer that has not been read out. The TXC flag must be cleared before each data transmission (before writing the transmit data register UDR)."
"The data register empty UDRE flag indicates whether the transmit buffer can accept a new data. This bit is set to "1" when the transmit buffer is empty; it is cleared when the transmit buffer contains data to be sent."
"When the entire data frame is shifted out of the transmit shift register and there is no new data in the transmit buffer, the transmit end flag TXC is set. TXC is automatically cleared when the transmission end interrupt is executed, and can also be cleared by writing "1" to this bit."
After reading the above instructions, I have been wondering whether I need to perform two operations at the same time when sending data:
1. Determine that UDRE is 1.
2. Clear the TXC mark.
However, the utilities I saw online did not have the second operation above, which seemed to work. With this doubt, I searched online and found a better answer:
"Regarding the AVR serial port, the explanation is as follows:
For transmission, there is a UDR buffer register and a shift register. When you write a UDR, the microcontroller immediately transfers the data to the shift register, so you can write the second data immediately. In the future, whenever the UDR buffer register is empty, a UDRE interrupt will be generated. To generate a TXC interrupt, you must wait until the data in the shift register has been sent.
For receiving, there are two UDR buffer registers and one shift register. The two receive buffers are equivalent to a FIFO structure. When there is data to be received, if a complete data is received into the shift register, it will be transferred to the buffer register. This will generate an RXC interrupt.
AVR is different from 51, so this structure is better. For example, when your program is busy in another interrupt, the serial port receives data. The two buffers will buy you time and will not lose data. The same is true for sending data. This is not the case with 51. "
"If you write two buffer data continuously, because the data just written to the buffer has been shifted to the shift register, you can write another data immediately. That is to say, when UDRE is set, the microcontroller still has a byte in the shift register being sent."
The conclusion is:
The common cyclic transmission program (i.e., the transmission program that only judges UDRE but not TXC) can work. The reason is the continuity of the transmitted data: that is, TXC=0 at the beginning, which meets the transmission conditions; when the data is continuously transmitted, because UDRE is set, there is still data in the shift register to be transmitted, so TXC is not set, which also meets the transmission conditions. TXC is not set until all data are sent and there is no data in the shift register and the transmission buffer.
have to be aware of is:
1. If a round of data has been sent before, the TXC flag must be cleared when sending again, that is, write "1" to this bit. It is best to detect the TXC flag and clear it after a round of data is sent.
2. If the transmit completion interrupt is used, there is no need to clear it manually, because after entering the transmit interrupt program, the hardware can automatically clear the TXC flag.
3. If interrupt transmission is not used but cyclic transmission is adopted, if the transmission program is suspended for more than a certain time due to other interrupts during the transmission process, the TXC flag bit will be set after the data in the shift register is sent, and subsequent transmission will be impossible.
4. If 485 is used for communication, the state of 485 will be changed only when TXC is detected to be set. Because only when TXC is set, it means that the sending process is completed.
I think the better sending procedure is as follows:
void uart_putchar(unsigned char c)
{
while(!(UCSR0A&(1<
if(UCSR0A&(1<
UCSR0A|=(1<
UDR0 = c;
}
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