Five working types of AVR microcontroller timer

5 types of work

Normal mode WGM1 = 0 is similar to the normal mode of 51, with TOV1 overflow interrupt flag, which occurs when MAX (0xFFFF)

1. Use the internal counting clock for ICP capture input occasions - measuring pulse width/infrared decoding (the capture input function can work in multiple modes, not just the normal mode)

2. Use external counting pulse input for counting, frequency measurement and other applications. It is more convenient to use other modes without the trouble of 51.

Dual CTC mode [Compare match clear timer mode] WGM1=4, 12 is similar to 51 in auto-reload mode

1. Used to output square wave signal with 50% duty cycle

2. Used to generate accurate continuous timing signal. When WGM1=4, the maximum value is set by OCR1A, and the OCF1A compare match interrupt flag is generated when TOP. When WGM1=12, the maximum value is set by ICF1, and the ICF1 input capture interrupt flag is generated when TOP.

If TOP = MAX, a TOV1 overflow interrupt flag will also be generated during TOP.

Note: When WGM=15, square wave output from OC1A can also be realized, and double buffer function is available.

Calculation formula: fOCn=fclk_IO/(2*N*(1+TOP)) The variable N represents the pre-division factor (1, 8, 64, 256, 1024), and T2 has two more levels (32, 128).

3. Fast PWM mode WGM1=5, 6, 7, 14, 15 single ramp counting, used to output high frequency PWM signal (twice the frequency of double ramp), all have TOV1 overflow interrupt, when it occurs in TOP [not MAX, different from normal mode and CTC mode], after comparison match, OCF1x comparison match interrupt can be generated.

When WGM1=5, the maximum value is 0x00FF, 8-bit resolution

When WGM1=6, the maximum value is 0x01FF, 9-bit resolution

When WGM1=7, the maximum value is 0x03FF, 10-bit resolution

When WGM1=14, the maximum value is set by ICF1, and an ICF1 input capture interrupt is generated at TOP (single buffer)

When WGM1=15, the maximum value is set by OCRF1A, and OCRF1A compare match interrupt is generated at TOP (double buffering, but OCRF1A will not have PWM capability and can only output square wave at most). When changing the TOP value, it must be ensured that the new TOP value is not less than the value of all compare registers.

Note that even if OCR1A/B is set to 0x0000, a narrow pulse of a timer clock cycle will be output instead of being always low.

Calculation formula: fＰＷＭ＝fｃｌｋ_ＩＯ／（N＊（１＋ＴＯＰ））

4. Phase correction PWM mode WGM1=1, 2, 3, 10, 11 dual ramp counting, used to output high-precision, phase-accurate, symmetrical PWM signals. All have TOV1 overflow interrupt, but when it occurs in BOOTOM, it can generate OCF1x compare match interrupt after compare match.

When WGM1=1, the maximum value is 0x00FF, 8-bit resolution

When WGM1=2, the maximum value is 0x01FF, 9-bit resolution

When WGM1=3, the maximum value is 0x03FF, 10-bit resolution

When WGM1=10, the maximum value is set by ICF1, and an ICF1 input capture interrupt is generated at TOP (single buffer)

When WGM1=11, the maximum value is set by OCRR1A, and OCFR1A compare match interrupt is generated at TOP (double buffering, but OCFR1A will not have PWM capability, and can only output square wave at most). When changing the TOP value, it must be ensured that the new TOP value is not less than the value of all comparison registers. A PWM signal with a duty cycle of 0% to 100% can be output. If the TOP value is to be changed during T/C operation, it is best to use the phase and frequency correction mode instead of the phase correction mode. If TOP remains unchanged, there is actually no difference between these two working modes.

Calculation formula: fＰＷＭ＝fｃｌｋ_ＩＯ／（２＊N＊ＴＯＰ）

5. Phase and frequency correction PWM mode WGM1=8,9 dual ramp counting is used to output high-precision PWM waveform with accurate phase and frequency. There is TOV1 overflow interrupt, but when it occurs in BOOTOM, OCF1x compare match interrupt can be generated after compare match.

When WGM1=8, the maximum value is set by ICF1, and an ICF1 input capture interrupt is generated at TOP (single buffer)

When WGM1=9, the maximum value is set by OCR1A, and an OCF1A compare match interrupt is generated at TOP (double buffering, but OCR1A will not have PWM capability and can only output square waves at most) Phase-frequency correction The main difference between the corrected PWM mode and the phase-corrected PWM mode is the update time of the OCR1x register. When changing the TOP value, it must be ensured that the new TOP value is not less than the value of all comparison registers. A PWM signal with a duty cycle of 0% to 100% can be output. When using a fixed TOP value, it is best to use the ICR1 register to define the TOP. In this way, OCR1A can be used to output a PWM wave at OC1A. However, if the PWM base frequency is constantly changing (by changing the TOP value), the double buffering feature of OCR1A makes it more suitable for this application.

Calculation formula: fＰＷＭ＝fｃｌｋ_ＩＯ／（２＊N＊ＴＯＰ）