A brief discussion on the T/C0 control register and T/C1 control register of ATmega 16 microcontroller

　　T/C0 related

　　1.TCCR0——T/C0 control register

　　FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00

　　Bit 7 - FOC0: Forced output compare bit.

　　FOC0 is only valid when WGM［01:00］ is set to non-PWM mode. To ensure compatibility with future devices, when using PWM, TCCR0 must be cleared when writing to it. After writing 1 to it, the comparison operation will be performed immediately. The compare match output pin OC0 will output the corresponding level according to the setting of COM［01:00］. It should be noted that FOC0 is like a latch signal, and it is the setting of COM［01:00］ that really works to force the output comparison. FOC0 will not cause any interrupts, nor will it be cleared in CTC mode using OCR0 as TOP. The return value of reading FOC0 is always 0.

　　Bit 6, Bit 3 - WGM [01:00]: Waveform generation mode

　　These two bits control the counting sequence, the maximum value of the counter and the waveform generated. The modes supported by T/C0 are: normal mode, clear counter mode (CTC) when compare match occurs, and two PWM modes, see the table below for details:

　　Mode WGM01 WGM00 T/C TOP OCR0 TOV0

　　(CTC0) (PWM0) Working mode update time setting moment

　　0 0 0 Normal 0xFF Immediate update 0xFF

　　1 0 1 Correct PWM 0xFF 0xFF 0x00

　　2 1 0 CTC OCR0 immediately updates 0xFF

　　3 1 1 Fast PWM 0xFF 0xFF 0xFF

　　Bit 5, Bit 4——COM［01:00］: Compare match output mode

　　These bits determine the level of the output pin OC0 when a compare match occurs. If one or all of COM[01:00] are set, OC0 works as a compare match output. At the same time, its direction control bit must be set to 1 to enable the output driver.

　　When OC0 is connected to a physical pin, the function of COM[01:00] depends on the setting of WGM[01:00].

　　Comparison output mode, non-PWM mode

　　COM01 COM00 Description

　　0 0 Normal port operation, no physical connection to OC0 pin

　　0 1 OC0 is inverted when a compare match occurs

　　1 0 OC0 is cleared when a compare match occurs

　　1 1 OC0 is set when a compare match occurs

　　Comparison output mode, fast PWM mode

　　COM01 COM00 Description

　　0 0 Normal port operation, no physical connection to OC0 pin

　　0 1 Reserved

　　1 0 When a compare match occurs, OC0 will be cleared, and when the count reaches 0XFF, OC0 will be set.

　　1 0 OC0 will be set when a compare match occurs, and OC0 will be cleared when the count reaches 0XFF

　　Comparison output mode, phase correction PWM mode

　　COM01 COM00 Description

　　0 0 Normal port operation, no physical connection to OC0 pin

　　0 1 Reserved

　　1 0 When a compare match occurs during an upward count, OC0 will be cleared, and when a compare match occurs during a downward count, OC0 will be set.

　　1 0 OC0 will be set when a compare match occurs during upward counting, and OC0 will be cleared when a compare match occurs during downward counting.

　　Bit [2:0] - CS [02:00]: Clock selection

　　Used to select the clock source of Timer/Counter0.

　　CS02 CS01 CS00 Description

　　0 0 0 No clock, T/C does not work

　　0 0 1 clk/1 (no prescaler)

　　0 1 0 clk/8 (from pre-)

　　0 1 1 clk/64 (from prescaler)

　　1 0 0 clk/256 (from prescaler)

　　1 0 1 clk/1024 (from prescaler)

　　1 1 0 The clock is input by the T0 pin, and the falling edge is triggered

　　1 1 1 The clock is input by T0 pin, rising edge triggered

　　2.TCNT0——T/C0 counting register

　　3.OCR0——Output Compare Register

　　4. TI MSK——T/C interrupt mask register

　　OCIE2 TOIE2  TI CE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0

　　Bit 1 - OCIE0: Timer/Counter0 output compare match interrupt enable bit. When OCIE0 and the global interrupt enable bit I of the status register are both "1", the Timer/Counter0 output compare match interrupt is enabled. When a compare match of Timer/Counter0 occurs, that is, when OCF0 in the TIFR is set, an output compare match interrupt is generated .

　　Bit 0 - TOIE0: Timer/Counter 0 overflow interrupt enable. When TOIE0 and the global interrupt enable bit I of the status register are both "1", the Timer/Counter 0 overflow interrupt is enabled. When the Timer/Counter 0 overflows, that is, the TOV0 bit in the TIFR is set, an overflow interrupt is generated .

　　5.TIFR——T/C Interrupt Flag Register

　　OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0

　　Bit 1 - OCF0: Timer/Counter0 Output Compare Flag Bit 0. OCF0 is set when the Timer/Counter0 matches the value of OCR0 (Output Compare Register 0). This bit is cleared by hardware in the interrupt service routine, and can also be cleared by writing 1 to it. When Bit I in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and OCF0 are all set, the interrupt service routine is executed.

　　Bit 0 - TOV0: Timer/Counter 0 overflow flag. TOV0 is set when the Timer/Counter 0 overflows. This bit is cleared by hardware when the corresponding interrupt service routine is executed. In addition, TOV0 can also be cleared by writing 1. The interrupt service routine is executed when Bit I in SREG, TOIE0 (Timer/Counter 0 overflow interrupt enable), and TOV0 are all set. Note: In phase-corrected PWM mode, TOV0 is set when the Timer/Counter 0 changes counting direction at 0x00.

　　6.SFIOR——Special Function Register

　　ADTS2 ADTS1 ADTS0 —— ACME PUD PSR2 PSR10

　　Bit 0 - PSR0: Prescaler reset for Timer/C1 and Timer/C0. When PSR10 is set, the prescaler for Timer/C1 and Timer/C0 is reset. This bit is cleared by hardware after the operation is completed. Writing to the world will not cause any operation. Timer/C1 and Timer/C0 share this prescaler, and the prescaler reset affects both timers. Reading this bit always returns 0.

　　T/C1 related registers

　　1.TCCR1A——Timer/C1 control register

　　COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10

　　Bit 7:6 – COM1A [1:0]: Comparison output mode of channel A

　　Bit 5:4 – COM1B [1:0]: Comparison output mode of channel B

　　Comparison output mode, non-PWM mode

　　COM1A1 COM1A0 Description

　　COM1B1 COM1B0

　　0 0 Normal port operation, no physical connection to OC1A/OC1B pins

　　0 1 OC0 is inverted when a compare match occurs

　　1 0 OC0 is cleared when a compare match occurs

　　1 1 OC0 is set when a compare match occurs

　　Comparison output mode, fast PWM mode

　　COM1A1 COM1A0 Description

　　COM1B1 COM1B0

　　0 0 Normal port operation, no physical connection to OC1A/OC1B pins

　　0 1 WGM［3:0］=15: OC1A is inverted when compare matches, and OC1B does not occupy a physical pin.

　　When WGM［3:0］ is other values, it is normal port operation, not OC1A/OC1B function

　　1 0 When a compare match occurs, OC1A/OC1B will be cleared, and when the count reaches 0XFF, OC1A/OC1B will be set.

　　1 1 When a compare match occurs, OC1A/OC1B will be set, and when the count reaches 0XFF, OC1A/OC1B will be cleared

　　Comparison output mode, phase correction PWM mode and phase frequency correction PWM mode

　　COM01 COM00 Description

　　0 0 Normal port operation, no physical connection to OC1A/OC1B pins

　　0 1 WGM13:0 = 9 or 14: OC1A is inverted when compare matches, and OC1B does not occupy a physical pin.

　　When WGM13:0 is other values, it is normal port operation, not OC1A/OC1B function

　　1 0 When counting in ascending order, the comparison match will clear OC1A/OC1B.

　　When counting in descending order, the comparison match will set OC1A/OC1B

　　1 1 When counting in ascending order, the compare match will set OC1A/OC1B.

　　When counting in descending order, the comparison match will clear OC1A/OC1B

　　Bit 3 – FOC1A: Channel A Forced Output Compare

　　Bit 2 – FOC1B: Channel B Forced Output Compare

　　FOC1A/FOC1B is activated only when WGM[13:10] specifies non-PWM mode. To be compatible with future devices, these two bits must be cleared when writing to TCCR1A in PWM mode. When the FOC1A/FOC1B bit is set to 1, the waveform generation unit is immediately forced to compare and match. The setting of COM1X[1:0] changes the output of OC1A/OC1B. Note that the FOC1A/FOC1B bit acts as a select signal. The value of the COM1x1:0 bit determines the effect of the forced comparison.

　　In CTC mode, using OCR1A as the TOP value, FOC1A/FOC1B gating will neither generate an interrupt nor clear the timer.

　　The FOC1A/FOC1B bits always read as 0.

　　Bit 1:0 – WGM1 [1:0]: Waveform generation mode

　　These two bits are combined with WGM[13:12] in the TCCR1B register to control the counting sequence of the counter - the upper limit of the counter count and determine the operating mode of the waveform generator. The operating modes supported by the T/C are: normal mode (counter), clear timer on compare match (CTC) mode, and three pulse width modulation (PWM) modes.

　　Mode WGM13 WGM12 WGM11 WGM10 Timer/Counter Upper Limit Value OCR1x Change OV1 Set

　　(CTC1) (PWM11) (PWM10) Operation mode limit TOP New time T time

　　0 0 0 0 0 Normal mode 0xFFFF Immediate update 0xFFFF

　　1 0 0 0 1 8-bit phase-corrected PWM 0x00FF TOP 0x0000

　　2 0 0 1 0 9-bit phase-corrected PWM 0x01FF TOP 0x0000

　　3 0 0 1 1 10-bit phase-corrected PWM 0x03FF TOP 0x0000

　　4 0 1 0 0 CTC OCR1A immediately updates 0xFFFF

　　5 0 1 0 1 8-bit fast PWM 0x00FF TOP TOP

　　6 0 1 1 0 9-bit fast PWM 0x01FF TOP TOP

　　7 0 1 1 1 10-bit fast PWM 0x03FF TOP TOP

　　8 1 0 0 0 Phase frequency correction PWM ICR1 0 0X0000

　　9 1 0 0 1 Phase frequency correction PWM OCR1A 0 0X0000

　　10 1 0 1 0 Phase correction PWM ICR1 TOP 0X0000

　　11 1 0 1 1 Phase correction PWM OCR1A TOP 0X0000

　　12 1 1 0 0 CTC ICR1 immediately updates 0XFFFF

　　13 1 1 0 1 Reserved – – –

　　14 1 1 1 0 Fast PWM ICR1 TOP TOP

　　15 1 1 1 1 Fast PWM OCR1A TOP TOP

　　2.TCCR1B——Timer/C1 Control Register

　　ICNC1 ICES1 —— WGM13 WGM12 CS11 CS10

　　Bit 7 – ICNC1: Input capture noise rejection enable bit.

　　Setting ICNC1 will enable the input capture noise suppression function. At this time, the input of the external pin ICP1 is filtered. Its function is to continuously sample 4 times from the ICP1 pin. If the 4 sampled values ​​are equal, the signal is sent to the edge detector. Therefore, enabling this function causes the input capture to be delayed by 4 clock cycles.

　　Bit 6 - ICES1: Input capture trigger edge selection

　　This bit selects which edge on ICP1 is used to trigger the capture event. ICES1 is "0" to select the falling edge to trigger the input capture; ICES1 is "1" to select the rising edge of the logic level to trigger the input capture. After an event is captured according to the setting of ICES1, the value of the counter is copied to the ICR1 register. The capture event is also set to ICF1. If the interrupt is enabled at this time, the input capture event is triggered. When ICR1 is used as the TOP value (see the description of the WGM[13:10] bits in the TCCR1A and TCCR1B registers), ICP1 is disengaged from the input capture function, so that the input capture function is disabled.