ARM exceptions and interrupts

Publisher:艺泉阁Latest update time:2019-12-24 Source: elecfans Reading articles on mobile phones Scan QR code
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1 SWI interrupt processing steps:

1) When entering an interrupt, pc->lr, cpsr->spsr, and cpsr_mode are set to privileged mode, all of which are completed by hardware.

2) Registering the interrupt vector table is done by software. You can use the B instruction or the ldr and dcd tables to place a jump instruction at the interrupt vector to jump to the interrupt handler.

3) The main purpose of the first-level interrupt handler is to obtain the swi number according to the arm or thumb status, and pay attention to saving registers and returning during the process.

4) The secondary interrupt handler can be written in C or assembly. It is mainly a branch structure that does the corresponding thing according to the interrupt number. It can be implemented using function pointers.


-----When using soft interrupts in an application, you can use the __swi (armcc only) keyword to declare the soft interrupt function, and automatically obtain the interrupt number when calling it.


2 IRQ interrupt based on s3c2410

First, here is a picture taken directly from the chip manual.

The previous subsrcpnd srcpnd intpnd are all SFRs provided by Samsung, which are implemented inside the chip. Their clearing method is quite special, which is to assign 1 to the corresponding bit. Considering that the setting method of external interrupts can only be driven by external events, this is not difficult to understand.


When an interrupt is sent to irq, the processing steps are as follows:

1 Check and jump to the exception vector table 0x18, take a jump instruction, and jump to the first-level irq interrupt processing function.

2 The task of the first-level interrupt handling function is to check the offset number of the interrupt source through the intoffset register, and then get the address of the second-level interrupt handling function according to the offset number and the base address, assign this address to pc, and then jump to the second-level interrupt handling function.

3 The secondary interrupt handling function may also need to check the corresponding register to obtain the specific interrupt source and then perform corresponding processing.

4 Interrupt return, because the user state cpsr has been pushed into spsr when entering the interrupt, it can be directly restored using the format of subs pc, lr, 4. Restore the original register mode and state.


to be continued. . .

Reference address:ARM exceptions and interrupts

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