I2C Interface Summary

1 Characteristics of I2C bus

The main advantages of the I2C bus are its simplicity and effectiveness. Since the interface is directly on the components, the I2C bus takes up very little space, reducing the space on the circuit board and the number of chip pins, reducing the cost of interconnection. The bus can be up to 25 feet long, usually with a maximum frequency of 400Khz, and can support 40 components at a maximum transmission rate of 10Kbps. Another advantage is that it supports multi-master control, where any device that can send and receive can become the master bus. A master can control the transmission of signals and the clock frequency. Of course, there can only be one master at any point in time.

2 I2C Serial Bus Overview

The I2C bus is a serial bus introduced by PHLIPS. It is a high-performance serial bus with bus arbitration and high- and low-speed device synchronization functions required by multi-host systems.

The I2C bus has only two bidirectional signal lines, one is the data line SDA, and the other is the clock line SCL.

The I2C bus is connected to the positive power supply through a pull-up resistor. When the bus is idle, both lines are high. A low level output by any device connected to the bus will make the bus signal low, that is, the SDA and SCL of each device are in a line "AND" relationship.

Each device connected to the I2C bus has a unique address. Data transmission between the host and other devices can be done by the host sending data to other devices. In this case, the host is the transmitter. The device that receives data on the bus is the receiver.

In a multi-host system, there may be several hosts trying to start the bus to transfer data at the same time. In order to avoid confusion, the I2C bus must go through bus arbitration to decide which host controls the bus.

3 Bus data transmission

3.1 Data bit validity rules

When the I2C bus is transmitting data, the data on the data line must remain stable while the clock signal is at a high level. The high or low level state of the data line is allowed to change only when the signal on the clock line is at a low level.

3.2 Start and stop signals

When the SCL line is at a high level, the change of the SDA line from a high level to a low level indicates a start signal; when the SCL line is at a high level, the change of the SDA line from a low level to a high level indicates a stop signal.

Both the start and stop signals are sent by the host. After the start signal is generated, the bus is in an occupied state; after the stop signal is generated, the bus is in an idle state.

Devices connected to the I2C bus can easily detect the start and end signals if they have a hardware interface for the I2C bus. For some microcontrollers that do not have a hardware interface for the I2C bus, in order to detect the start and end signals, it is necessary to ensure that the data line SDA is used twice in each clock cycle.

After receiving a complete data byte, the receiving device may need to complete some other work, such as processing internal interrupt services, and may not be able to receive the next byte immediately. At this time, the receiving device can pull the SCL line to a low level, so that the host is in a waiting state. When the receiving device is ready to receive the next byte, the SCL line is released to a high level, so that data transmission can continue.

3.3 Data transmission format

3.3.1 Byte Transmission and Response

Each byte must be 8 bits long. When data is transmitted, the most significant bit (MSB) is transmitted first, and each transmitted byte must be followed by an acknowledge bit (i.e., a frame has a total of 9 bits).

When the slave does not respond to the host addressing signal for some reason (such as the slave is performing real-time processing and cannot receive data on the bus), it must set the data to a high level, and the host generates a termination signal to end the bus data transmission.

If the slave responds to the host but cannot receive more data after a period of data transmission, the slave can notify the host by "non-response" to the first data byte that cannot be received, and the host should send a termination signal to end the continued transmission of data.

When the master receives data, it must send a signal to the slave to end the transmission after receiving the last data byte. This signal is implemented by a "non-acknowledge" to the slave. However, the slave releases the SDA line to allow the master to generate a termination signal.

3.3.2 Data frame format

The data signals transmitted on the I2C bus are broad in nature, including both address signals and actual data signals.

After the start signal, a slave address (7 bits) must be transmitted. The 8th bit is the data transmission direction bit (R/). "0" indicates that the host sends data (T), and "1" indicates that the host receives data (R). Each data transmission is always terminated by the termination signal generated by the host. However, if the host wants to continue to occupy the bus for new data transmission, it can not generate a termination signal and immediately initiate a start signal again to address another slave.

During a data transmission process on the bus, there can be the following combinations:

    (1) The host sends data to the slave, and the data transmission direction remains unchanged during the entire transmission process

Note: The shaded part indicates data is transmitted from the host to the slave, and the unshaded part indicates data is transmitted from the slave to the host. A indicates response, and indicates non-response (high level). S indicates the start signal, and P indicates the end signal.

(2) After sending the first byte, the host immediately reads the slave data

(3) During the transmission process, when the transmission direction needs to be changed, the start signal and the slave address are generated once, but the read/write direction bits are exactly reversed;

3.4 Bus Addressing

The I2C bus protocol has clear provisions: use a 7-bit addressing byte (the addressing byte is the first byte after the start signal).

3.4.1 Addressing byte definition

D7 to D1 constitute the slave address. D0 is the data transfer direction bit. When it is "0", it means the host writes data to the slave, and when it is "1", it means the host reads data from the slave.

When the master sends an address, each slave on the bus compares the 7-bit address with its own address. If they are the same, it believes that it is being addressed by the master and identifies itself as a transmitter or receiver based on the R/ bit.

The address of the slave consists of a fixed part and an editable part. In a system, you may want to connect multiple identical slaves. The programmable part of the slave address determines the maximum number of devices of this type that can be connected to the bus. For example, if 4 of the 7-bit addressing bits of a slave are fixed bits and 3 are programmable bits, then only 8 identical devices can be addressed, that is, 8 identical devices can be connected to the I2C bus system.

3.4.2 Special Addresses in Addressing Bytes

Fixed address numbers 0000 and 1111 are reserved for special purposes

When the 8 bits of the first byte after the start signal are "0000 0000", it is called the general call address. The purpose of the general call address is explained in the second byte. The format is:

When the second byte is 06H, all slave devices that can respond to the general call address are reset and the programmable part of the slave address is loaded by hardware. When the slave devices that can respond to the command are reset, the SDA and SCL lines are not pulled low to avoid blocking the bus.

When the second byte is 04H, all slave devices that can respond to the general call address and define their programmable addresses through hardware will lock the programmable bits in the address but will not reset.

If the direction bit B of the second byte is "1", the two-byte command is called a hardware general call command.

The high 7 bits of the second byte describe its own address. Intelligent devices connected to the bus, such as single-chip microcomputers or other microprocessors, can recognize this address and transmit data to it. When the hardware master device is used as a slave, this address is also used as the slave address. The format is:

Another option in the system may be that the hardware host device works in slave receiver mode when the system is reset. At this time, the host in the system first tells the hardware host device the address of the slave device to which the data should be sent. When the hardware host device wants to send data, it can send data directly to the specified slave device.