IICvs SPI
Nowadays, in the field of low-end digital communication applications, we can see IIC (Inter-Integrated Circuit) and SPI (Serial Peripheral Interface) everywhere. The reason is that these two communication protocols are very suitable for short-distance and low-speed inter-chip communication. Philips (for IIC) and Motorola (for SPI) developed these two standard communication protocols due to different backgrounds and market needs.
IIC was developed in 1982 to provide a simpler way to interconnect the CPU and peripheral chips in televisions. Televisions were one of the earliest embedded systems, and the original embedded systems used memory-mapped I/O to interconnect microcontrollers and peripherals. To achieve memory mapping, the device must be connected in parallel to the data and address lines of the microcontroller. This method requires a large number of lines and additional address decoding chips when connecting multiple peripherals, which is inconvenient and costly.
In order to save microcontroller pins and additional logic chips, make printed circuit boards simpler and less expensive, Philips Laboratories in the Netherlands developed 'Inter-Integrated Circuit', IIC or IIC, a bus protocol that uses only two wires to connect all peripheral chips. The initial standard defines the bus speed as 100kbps. It has undergone several revisions, mainly 400kbps in 1995 and 3.4Mbps in 1998.
There are indications that the SPI bus was first introduced in 1979, when Motorola integrated the SPI bus into their first microcontroller chip, which was modified from the 68000 microprocessor. The SPI bus is a four-wire external bus (as opposed to an internal bus) of a microcontroller. Unlike IIC, SPI has no explicit standard, but is a de facto standard that only provides a general abstract description of the implementation of communication operations. Chip manufacturers and driver developers communicate the implementation details through data sheets and application notes.
SPI
For experienced digital electronics engineers, interconnecting two digital devices using SPI is quite intuitive. SPI is a four-wire protocol (see figure):
§ SCLK: Serial Clock (output from master);
§ MOSI; SIMO: Master Output, Slave Input(output from master);
§ MISO; SOMI: Master Input, Slave Output(output from slave);
§ SS: Slave Select (active low, outputfrom master).
SPI is a [single-master] communication protocol, which means that only one central device in the bus can initiate communication. When the SPI master device wants to read/write the [slave device], it first pulls down the SS line corresponding to the [slave device] (SS is low level valid), and then starts sending working pulses to the clock line. At the corresponding pulse time, the [master device] sends the signal to MOSI to achieve "write", and can sample MISO to achieve "read", as shown below:
SPI has four operating modes - Mode 0, Mode 1, Mode 2 and Mode 3. The difference between them is that they define which edge of the clock pulse toggles the output signal, which edge samples the input signal, and the stable level value of the clock pulse (that is, whether the clock signal is high or low when it is invalid). Each mode is characterized by a pair of parameters, which are called clock polarity CPOL and clock phase CPHA.
The master and slave devices must use the same operating parameters - SCLK, CPOL and CPHA to work properly. If there are multiple slave devices and they use different operating parameters, the master device must reconfigure these parameters between reading and writing different slave devices. The above are the main contents of the SPI bus protocol. SPI does not specify the maximum transmission rate, there is no address scheme; SPI does not specify the communication response mechanism, and there is no flow control rule. In fact, the SPI master device does not even know whether the specified slave device exists. These communication controls must be implemented by themselves outside the SPI protocol. For example, to use SPI to connect a command-response control type decoding chip, a more advanced communication protocol must be implemented on the basis of SPI. SPI does not care about the electrical characteristics of the physical interface, such as the standard voltage of the signal. In the beginning, most SPI applications used intermittent clock pulses and transmitted data in bytes, but now there are many variants that implement continuous time pulses and data frames of arbitrary length.
IIC
Unlike SPI's single-master device, IIC is a multi-master device bus. IIC has no physical chip select signal line, no arbitration logic circuit, and only uses two signal lines - 'serial data' (SDA) and 'serial clock' (SCL). The IIC protocol stipulates:
§ First, each IIC device has a unique seven-bit device address;
§ Second, the data frame size is 8-bit byte;
§ Third, certain bits in the data (frame) are used to control the start, stop, direction (read or write), and acknowledgment mechanisms of the communication.
IIC data rates include standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps), with some variants implementing low-speed mode (10 kbps) and fast-plus mode (1 Mbps).
In physical implementation, the IIC bus consists of two signal lines and a ground line. Both signal lines are bidirectional, see the figure below. The IIC protocol standard stipulates that the device that initiates communication is called the master device. After the master device initiates a communication, other devices are slave devices.
The IIC communication process is as follows. First, the master device sends a START signal, which is like shouting to all other devices: Attention, everyone! Then other devices start to monitor the bus to prepare to receive data. Next, the master device sends a data frame of a 7-bit device address plus one bit for read and write operations. When the device receives the data, it compares the address to see if it is the target device. If the comparison does not match, the device enters the waiting state and waits for the arrival of the STOP signal; if the comparison matches, the device will send an acknowledgment signal - ACKNOWLEDGE in response.
When the master device receives the response, it starts to transmit or receive data. The data frame size is 8 bits, followed by a one-bit response signal. The master device sends data and the slave device responds; conversely, the master device receives data and the master device responds. When the data transmission is completed, the master device sends a STOP signal to announce the release of the bus to other devices, and other devices return to the initial state.
Based on the physical structure of the IIC bus, the START and STOP signals on the bus must be unique. In addition, the IIC bus standard stipulates that the data conversion of the SDA line must be during the low level period of the SCL line, and the data on the SDA line is stable during the high level period of the SCL line.
In physical implementation, both the SCL line and the SDA line are open-drain, and a voltage source is added through a pull-up resistor. When the line is grounded, the line is logic 0, and when the line is released and the line is idle, the line is logic 1. Based on these characteristics, the IIC device's operation on the bus is only "grounding the line" - outputting logic 0.
The IIC bus design uses only two wires, but it is quite elegant to achieve seamless communication between any number of devices, which is perfect. Let's imagine what will happen if two devices send information to the SCL line and SDA line at the same time.
Based on the design of the IIC bus, there is no possibility of level conflict on the line. If one device sends logic 0 and the other sends logic 1, then the line only sees logic 0. In other words, if there is a level conflict, the one sending logic 0 is always the "winner".
The physical structure of the bus also allows a master device to read data while writing data to the bus. In this way, any device can detect the occurrence of a conflict. When two master devices compete for the bus, the "winner" is unaware of the competition. Only the "loser" discovers the conflict - when it writes a logical 1 but reads a 0 - and withdraws from the competition.
10-bit device address
Any IIC device has a 7-bit address. In theory, there can only be 127 different IIC devices in reality. In reality, there are far more types of IIC devices than this limit, and the probability of IIC devices with the same address appearing on a bus is quite high. In order to break through this limitation, many devices use dual addresses - 7-bit address plus pin address (external configuration pins). The IIC standard also anticipated this limitation and proposed a 10-bit address scheme.
The 10-bit address scheme has two effects on the IIC protocol:
§ First, the address frame is two bytes long, instead of one byte;
§ Second, the first five most significant bits of the first byte are used as a 10-bit address identifier, and the convention is "11110".
In addition to the 10-bit address identifier, the standard also reserves some address codes for other purposes, as shown in the following table:
Clock stretching
In IIC communication, the master device determines the clock speed. Because the clock pulse signal is explicitly sent by the master device. However, when the slave device cannot keep up with the speed of the master device, the slave device needs a mechanism to request the master device to slow down. This mechanism is called clock stretching, and it is implemented based on the particularity of the I²C structure. When the slave device needs to reduce the transmission speed, it can press the clock line, forcing the master device to enter a waiting state until the slave device releases the clock line, and communication continues.
High-speed mode
In principle, using pull-up resistors to set logic 1 limits the maximum transmission speed of the bus. Speed is one of the factors that limit bus applications. This also explains why the high-speed mode (3.4 Mbps) was introduced. Before initiating a high-speed mode transmission, the master device must first send a specific "High Speed Master" signal in a low-speed mode (such as fast mode). In order to shorten the signal cycle and increase the bus speed, the high-speed mode must use additional I/O buffers. In addition, bus arbitration can be masked in high-speed mode. For more information, please refer to the bus standard document.
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Recommended ReadingLatest update time:2024-11-16 14:55
Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
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