ARM interrupt architecture

Seven modes of operation of ARM architecture CPU

User mode (usr): the normal program execution state of the ARM processor

System mode (sys): runs privileged operating system tasks

Management mode (svc): protection mode used by the operating system

Interrupt mode (irq): used for general interrupt processing

Fast interrupt mode (fiq): used for high-speed data transmission or channel processing

Data access termination mode (abt): The mode entered when data or instruction prefetching is terminated

Undefined mode (und): When an undefined instruction is executed, this interrupt is entered

ARM register introduction

ARM920T has 31 general registers and six program status registers, a total of 37 divided into 7 groups, corresponding to the seven working modes of the above CPU.

Each operating mode has 16 general-purpose registers and 1 (or 2) program status registers.

User mode and system mode 

The registers for these two modes are the same, there are 16 general registers (R0-R15) and a program status register (CPSR). 

R13 is called the stack pointer register 

R14 is called the link register ->> when the program BL subroutine, it is used as a backup for R15 when an error occurs 

R15 is called the program counter 

cpsr is called program status register

Program Status Register CPSR

The cpsr program status register is a register used to record the current processor status. There is one cpsr for each of the seven processing modes. That is to say, the ARM architecture processor has only one cpsr, but in addition to the five modes of usr and sys, there is also a backup register of the cpsr, SPSR.

cpsr is 32 bits 

31 30 29 28 27. . . . . 8 7 6 5 4 3 2 1 0 

NZCV…………………….IFT M4 M3 M2 M1 M0 

High four bits (28-31): condition flag bits 

- Whether the result of N is negative 

- Whether the Z structure is 0 

- C Carry/Borrow/Shift Overflow 

- V overflow flag 

Middle 20 (27-8): Reserved 

Lower 8 bits (7-0): control bits 

- I interrupt disable bit 

- F Fast interrupt disable bit 

-T cpu status bit 

- M0/M1/M2/M3 operating mode bits