Introduction to AMBA, AHB and APB in stm32

AMBA (Advanced Microcontroller Bus Architecture) is an on-chip bus introduced by ARM. The AMBA specification mainly includes: AHB (Advanced High-performance Bus) system bus and APB (Advanced Peripheral Bus) peripheral bus. Among them, the interconnection of AHB adopts the traditional shared bus with master module and slave module, and the interface and interconnection functions are separated, which is of great significance for the interconnection between modules on the chip. AMBA is not only a bus, but also an interconnection system with interface modules.

AMBA-based System-on-Chip

   A typical system block diagram based on AMBA bus is shown in Figure 3.

    Most modules (including processors) on the bus are functional modules with a single attribute: master or slave. The master module is the module that issues read and write operations to the slave module, such as the CPU, DSP, etc. The slave module is the module that receives commands and responds, such as the on-chip RAM, AHB/APB bridge, etc. In addition, some modules have both attributes. For example, direct memory access (DMA) is a slave module when it is programmed, but it must be a master module when the system reads and transmits data. If there are multiple master modules on the bus, an arbitrator is needed to decide how to control the access of various master modules to the bus. Although the arbitration specification is part of the AMBA bus specification, the specific algorithm used is determined by the RTL design engineer. The two most commonly used algorithms are the fixed priority algorithm and the round-robin algorithm. There can be up to 16 master modules and any number of slave modules on the AHB bus. If the number of master modules is greater than 16, an additional layer of structure is required (see the Multi-layer AHB specification launched by ARM for details). The APB bridge is both the only master module on the APB bus and a slave module on the AHB system bus. Its main function is to latch the address, data and control signals from the AHB system bus, and provide secondary decoding to generate selection signals for APB peripheral devices, thereby realizing the conversion from AHB protocol to APB protocol.

About AHB

    AHB is mainly used for the connection between high-performance modules (such as CPU, DMA and DSP, etc.). As the on-chip system bus of SoC, it includes the following features: single clock edge operation; non-three-state implementation; support burst transmission; support segmented transmission; support multiple master controllers; configurable 32-bit to 128-bit bus width; support byte, half-byte and word transmission. The AHB system consists of three parts: master module, slave module and infrastructure. The transmission on the entire AHB bus is issued by the master module and responded by the slave module. The infrastructure consists of an arbiter, a multiplexer from the master module to the slave module, a multiplexer from the slave module to the master module, a decoder, a dummy slave module, and a dummy master module. Its interconnection structure is shown in Figure 1.

APB Introduction

    APB is mainly used for the connection between low-bandwidth peripherals, such as UART, 1284, etc. Its bus architecture does not support multiple master modules like AHB. The only master module in APB is the APB bridge. Its features include: two clock cycle transmission; no waiting cycle and response signal; simple control logic, only four control signals. The transmission on APB can be explained by the state diagram shown in Figure 2.

     1) The system is initialized to IDLE state. There is no transmission operation and no slave module is selected.

     2) When there is a transmission to be carried out, PSELx = 1, PENABLE = 0, the system enters the SETUP state, and will only stay in the SETUP state for one cycle. When the next rising edge of PCLK arrives, the system enters the ENABLE state.

     3) When the system enters the ENABLE state, the PADDR, PSEL, and PWRITE in the SETUP state are maintained unchanged, and PENABLE is set to 1. The transmission will only be maintained in the ENABLE state for one cycle, and it will be completed after passing through the SETUP and ENABLE states. If there is no transmission to be performed afterwards, it will enter the IDLE state to wait; if there is continuous transmission, it will enter the SETUP state.

    In STM32, the devices connected to APB1 (low-speed peripherals) are: power interface, backup interface, CAN, USB, I2C1, I2C2, UART2, UART3, SPI2, window watchdog, Timer2, Timer3, Timer4. The devices connected to APB2 (high-speed peripherals) are: GPIO_A-E, USART1, ADC1, ADC2, ADC3, TIM1, TIM8, SPI1, ALL.