DSP startup loading principle

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1. Scope of application

This document introduces the startup process of SylixOS on DSP. The relevant content introduced in this document is for TI official evaluation board TMDSEVM6678.

2. Introduction to DSP startup principle

When the DSP is restarted, the RBL (on-chip primary loader) will be executed first. The RBL is solidified in the on-chip ROM. The main function of the RBL is to determine the startup mode and load and run the UBL (user-written secondary loader) from the specified device. The main function of the UBL is to load the BSP program of SylixOS. When the BSP program is running, the application program can be developed through dynamic loading. As shown in Figure 2.1:

Figure 2.1 Basic startup process

3. DSP startup mode

DSP supports 11 boot modes. In the official evaluation board, SylixOS development mainly uses ROM SPI Boot mode and No boot mode. The mode configuration of the DIP switch is shown in Figure 3.1:

Figure 3.1 DIP switch configuration

The DSP startup modes are as follows (IBL is the UBL burned into the EEPROM):

• IBL NOR boot: IBL is in EEPROM, BSP is in NOR;

• IBL NAND boot: IBL is in EEPROM, BSP is in NAND;

• IBL TFTP boot: IBL is in EEPROM, BSP is obtained through TFTP;

• I2C POST boot: power-on self-test mode;

• ROM SPI Boot: UBL and BSP are both in SPI Flash;

• ROM SRIO Boot: UBL and BSP are loaded through SRIO;

• ROM Ethernet Boot: UBL and BSP are loaded through the network

• ROM PCIE Boot: UBL and BSP are loaded through PCIE

• No boot: Mainly used for solidification program, only this mode will perform initial operation through gel file

4. DSP BSP program loading

The BSP program of SylixOS is in elf format, so when UBL loads the BSP program, it will first parse the elf format and allocate the corresponding segments to different locations according to the configuration. When the BSP program runs successfully, you can develop applications through dynamic loading. The division of RAM by SylixOS is shown in Figure 4.1:

Figure 4.1 SylixOS RAM division

SylixOS places the different segments of the BSP program into the areas specified in the above figure, refer to Figure 4.2 for details.

Figure 4.2 Allocation of BSP segments