STM32 register access

General register access needs to be implemented through the three steps of read-modify-write and bit operations of clearing and setting. However, in the programming of STM32, by utilizing some of its excellent features such as port bit set/reset register BSRR, bit binding, etc., we can greatly improve the access speed of registers and simplify the operation of registers.

//General register operations:

GPIOx->ODR |= 0x10; //Pin4 set to 1

GPIOx->ODR &= ~0x10; //Pin4 cleared to 0

BSRR/BRR Register 

GPIOx->BSRR //Write 1 to set the lower 16 bits of BSRR, and write 1 to clear the upper 16 bits of BSRR

GPIOx->BRR //Write 1 to clear the lower 16 bits of BRR, and keep the upper 16 bits of BRR

It can be seen that operating the ODR register through the BSRR/BRR register does not require the three steps of read-modify-write. It can be done in one step by just writing, which is much more convenient.

Bit Binding 

Of course, stm32 has an even more powerful feature - bit binding, which can realize single bit operation in just one clock cycle. Bit binding is to map a bit in a register to a storage unit in memory through a simple address conversion. In this way, a bit of the corresponding register can be indirectly accessed by reading and writing a memory unit. Of course, at this time, only the lowest bit of the 32-bit memory unit is valid!

However, the entire M3 core does not allow bit binding, only two areas do, namely

SARM: 0x20000000~0x2000FFFF 1M size 

The address bound to this area starts from 0x22000000;  

PERIPHERALS: 0x40000000~0x4000FFFFF 1M size

The address bound to this area starts from 0x42000000;

The corresponding bit binding formula is:  

SRAM：AliasADDr = 0x22000000+((A-0x20000000)*32+n*4)

Where A: 0x20000000~0x2000FFFF n: 0~31

PERIPHERALS: AliasADDr = 0x42000000+((A-0x40000000)*32+n*4)

Where A: 0x40000000~0x4000FFFFF n: 0~31

Now we can quickly implement bit operations through bit binding 

#define GPIOA_ODR_ADDR (GPIOA_BASE + 0x0C)

#define GPIOA_IDR_ADDR (GPIOA_BASE + 0x08)

#define BitBind(Addr, bitNum) (*(volatile unsigned long *)((Addr&0xF0000000)+0x2000000+((Addr&0xFFFFF)<<5)+(bitNum<<2)))

//Addr&0xF0000000 is to distinguish SRAM or PERIPHERALS

//Addr&0xFFFFF is equivalent to (A-0x20000000) or (A-0x40000000)

//Left shift is to achieve fast multiplication operation: left shift n bits is equivalent to multiplying by 2^n

#define PAout(n) BitBind(GPIOA_ODR_ADDR, n) 

#define PAin(n) BitBind(GPIOA_IDR_ADDR, n)

This implements an operation similar to the 51 microcontroller access to I/O

sbit P10 = P1^0

P10 = 0; or P10 = 1;

PAout(3) = 1; or PAout(3) = 0;   

Pretty cool, huh!