Clock division of STM32-EEWORLD

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TIM_TimeBaseStructure.TIM_ClockDivision ；//Clock division

TIMx_CCMR1 Register

Fck_int is the input frequency of the timer (TIMxCLK), which is generally 72Mhz, and is determined by the setting of CKD[1:0] of TIMx_CR1. If CKD[1:0] is set to 00, then = . The N value is the filter length. For example, suppose IC1F[3:0]=0011, and set IC1 to be mapped to channel 1, and it is a rising edge trigger. When the rising edge is captured, the level of channel 1 is continuously sampled 8 times at a frequency of. If they are all high levels, it means that it is indeed a valid trigger, and the input capture interrupt will be triggered (if it is turned on). In this way, pulse signals with a high-level pulse width less than 8 sampling cycles can be filtered out, thereby achieving the filtering effect. {From the Zhengdian Atom Manual}

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