STM32F4——GPIO basic application and multiplexing

1. Basic IO structure:

    There are 7 groups of IO for STM32F407, namely GPIOA~GPIOG, each group of IO has 16 IO ports, so there are 112 IO ports. The basic structure of the IO port is as follows:

2. Working method:

    There are 8 working modes of STM32F4, including 4 input modes and 4 output modes, namely: input floating, input pull-up, input pull-down, analog mode, open-drain output, open-drain multiplexed output, push-pull output, and push-pull multiplexed output.

    1. Input mode:

        In input floating mode, the circuit does not pull up or pull down, and is sent to the input data register through the Schmitt trigger and then to the CPU. In input pull-up and pull-down modes, the circuit is pulled up and pulled down in the circuit and then sent to the CPU through the Schmitt trigger. In analog mode, after the Schmitt trigger is turned off, the signal is directly sent to the on-chip peripherals through the analog channel.

    2. Output mode:

        In the open-drain output mode, the CPU sends input to directly or indirectly control the output data register. Through the output control circuit, when the signal is 1, the N-MOS tube is closed, so the IO level is controlled by the pull-up and pull-down circuits. When the signal is 0, the N-MOS tube is turned on and the output is pulled down to a low level; in the push-pull output mode, when the signal is 1, the P-MOS tube is turned on and the N-MOS tube is turned off, and the output is pulled up to a high level. When the signal is 0, the P-MOS tube is turned off and the N-MOS tube is turned on, and the output is pulled down to a low level. The difference between the open-drain multiplexing and push-pull multiplexing modes and the open-drain and push-pull multiplexing modes is that the source of the signal is different. The signal source of the open-drain multiplexing and push-pull multiplexing is the on-chip peripheral module.

3. Related registers

    Each general IO port includes four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, PIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), one 32-bit position/reset register (GPIOx_BSRR), one 32-bit lock register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRL). They are introduced below.

    1. Working mode configuration: 1. Port mode (GPIOx_MODER): used to configure the port mode as input, output, multiplexing and analog mode. 2. Port type (GPIOx_OTYPER): used to configure the register mode as output push-pull or output open-drain. 3. Port speed (PIOx_OSPEEDR): used to configure the information transmission rate of the port. 4. Port pull-up and pull-down (GPIOx_PUPDR): used to configure the port mode of no pull-up and pull-down, pull-up, pull-down and reserved.

    2. Level configuration: 1. Input data (GPIOx_IDR): The lower 16 bits are used to correspond to a level state of the IO port of this group. 2. Output data (GPIOx_ODR): The function is similar to the input data register. 3. Set and reset (GPIOx_BSRR): The difference from the previous two is that the set and reset registers use 32 bits. When the lower 16 bits are set to 1, they are used to set the corresponding bit. When the upper 16 bits are set to 1, they are used to set the corresponding bit. When the lower 16 bits and the upper 16 bits are set to 0, the original value is not affected.

    3. Multiplexing function configuration: The corresponding instructions are given below.

IO multiplexing

1. Reuse Background:

    Considering the limited number of IO ports, in order to save IO resources and better coordinate the work between IO ports, it is necessary to assign different functions to IO ports at appropriate times. An IO port can undertake different tasks at different times. This is the multiplexing function of IO.

2. Reuse principle:

    Each IO port is connected to a selector. After the configuration of the corresponding registers (GPIOx_AFRH and GPIOx_AFRL), the selector can be used for different functions. The registers are GPIOx_AFRH and GPIOx_AFRL.

3. Register configuration:

    Each group of IO ports has an AFRL and an AFRH register, both of which are 32-bit registers, where each 4 bits configure the function of an IO port, and the corresponding GPIOx_AFRL is used to configure the 0th to 7th IO ports, and GPIOx_AFRH is used to configure the 8th to 15th IO ports. Each 4 bits configure an IO port, and the relevant values ​​of the 4-bit data will have corresponding corresponding functions. In this way, the relevant configuration is done.

Summary:

    These related configuration processes will use corresponding functions and corresponding variables. You will be more comfortable with the application only after you are proficient in using the related functions and understand their functions. You can also write some related functions of your own to perform operations. Of course, you can also directly operate the related registers.