How does STM32 enter the interrupt function xxx_IRQHandler

How does STM32 enter the interrupt function xxx_IRQHandler, such as: void USART1_IRQHandler(void) 
When I started to use STM32 some time ago, I encountered such a problem. When the interrupt settings are configured in the program, how does the program enter the interrupt function when it is running (of course, the interrupts mentioned here are all hardware interrupts), because when running a C program, my understanding is that you always have to have a "baton" or an "entrance" before it can enter the next function. Take 
uart1 configuration as an example, 
//Interrupt initialization 
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0); 
NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; 
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; 
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 
NVIC_Init(&NVIC_InitStructure);

/Serial port initialization 
USART_StructInit(&USART_InitStructure); //Serial port 1 uses default configuration 
USART_Init(USART1, &USART_InitStructure); //Initialize serial port 
USART_Cmd(USART1, ENABLE); //Enable serial port

USART_ITConfig(USART1, USART_IT_TXE, DISABLE); //Disable send buffer empty interrupt 
USART_ITConfig(USART1, USART_IT_TC , ENABLE); //Send complete interrupt 
USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); //Receive interrupt 
USART_ITConfig(USART1, USART_IT_IDLE, ENABLE); //Receive idle interrupt

When an interrupt occurs, the program responds to the interrupt service function void USART1_IRQHandler(void)  in stm32f10x_it.c 
{

#if OS_CRITICAL_METHOD == 3                      
    OS_CPU_SR cpu_sr = 0;
#endif
OS_ENTER_CRITICAL(); 
OSIntEnter();
OS_EXIT_CRITICAL();

UartISR(U1ART);
OSIntExit();12345678910

} 
So how does the program find it? In the startup file startup_stm32f10x_md.s, there is a piece of code that assembles 
DCD USART1_IRQHandler 
, where DCD is a data definition pseudo instruction, which is used to allocate a continuous word storage unit and initialize it with specified data. 
There are also some such as PUBWEAK USART1_IRQHandler, etc., the specific meaning is not very clear. 
The library defines #define USART1 ((USART_TypeDef *) USART1_BASE) 
and #define USART1_BASE (APB2PERIPH_BASE + 0x3800). 
My personal understanding is that when the control register interrupt enable of USART1 is configured, when an interrupt (exception) occurs, the exception is accepted by the Cortex-M3 core, and the corresponding exception Handler will be executed. And this response process is completed by hardware. Of course, in order to determine the entry address of the Handler, Cortex-M3 uses the "vector table lookup mechanism". The startup_stm32f10x_md.s startup file has assigned this address to USART1_IRQHandler. So after an exception occurs, the CPU enters the exception mode, and the program counter PC automatically points to the exception entry address, that is, USART1_IRQHandler, and then executes the application in the interrupt service function.