STM32F10XXX bus architecture and memory organization

1. Bus architecture

Taking the Internet large-capacity product as an example, the overall bus architecture is as follows:

in,

DCode, also known as D-bus, is a data bus as its name implies. It connects the data interface of Contex-M3 and flash memory through a bus matrix and can be used for constant loading (my understanding is RO DATA access) and debugging access (how to apply it is not known yet).

ICode, instruction bus, realizes the connection between Contex-M3 and the instruction interface of flash memory, and is used to read the program RO CODE (.text).

System, system bus, realizes the connection between the peripheral bus and the bus matrix. The built-in SRAM is accessed through the system bus.

DMA bus, connecting the AHB master interface of the DMA hardware to the bus matrix.

Bus Matrix: DMA can access SRAM, flash memory and peripherals through the DMA bus. We know that Contex-M3 can also access these data through the DCode or System bus. In order to prevent the two from conflicting, the bus matrix logic is required to arbitrate.

AHB is connected to the system bus through the bus matrix. Together with the AHB/APB bridge, it forms a channel to the peripherals. As can be seen from the above figure, APB is divided into two types: APB1 and APB2. This is to adapt to peripherals of different speeds while taking into account performance and power consumption. The operating frequency of APB1 is limited to 36MHz, and APB2 operates at full speed (up to 72MHz).

2. Memory organization

The flash, built-in SRAM, on-chip registers, etc. in the STM32F10XXX together form a 4GB linear address space. Data is stored in little-endian format, that is, the low byte is located at the low address (two lows are little-endian).

The following figure shows the mapping address of the on-chip peripheral registers, which is the source of the following type definition in the C program.

1. #define PERIPH_BB_BASE ((u32)0x42000000)  

2. #define SRAM_BB_BASE ((u32)0x22000000)  

3. #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)  

2.1 Let’s talk about the concept of bit-band

        It is actually a technology that already exists in 8051. It operates by mapping each bit of data in a certain address range to another address space. In this way, access to the mapped address is equivalent to accessing the bit before mapping.

The Cortex™-M3 memory map consists of two bit-band areas. They are:

0x2000_0000-0x200F_FFFF (lowest 1MB in the SRAM area) 
0x4000_0000-0x400F_FFFF (lowest 1MB in the on-chip peripheral area)

The two bit-band regions map each word in the alias memory region to a bit in the bit-band memory region. Writing a word in the alias memory region has the same effect as performing a read-modify-write (RCU) operation on the target bit in the bit-band region.
In the STM32F10xxx, both the peripheral registers and SRAM are mapped to a bit-band region, which allows single bit-band write and read operations. The following mapping formula shows how each word in the alias region corresponds to the corresponding bit in the bit-band region:
bit_word_addr = bit_band_base + (byte_offset×32) + (bit_number×4) 
Where:

The multiplication constants 32 and 4 are because the mapped address is 4-byte aligned.
bit_word_addr is the address of the word in the alias memory area that is mapped to a target bit.  bit_band_base is the starting address of the alias area. byte_offset is the number of the byte in the bit band that contains the target bit 
.  bit_number is the position of the target bit (0-31)

Advantages of using bit-band:

1. Directly operate the bit position, and increase the control of GBIO port and other registers.

2. RCU is an atomic operation that implements mutually exclusive access to resources.

3. Make the code bid more concise.

You can use the bit-band function in C statements. You can directly #define the mapped address area, such as:

1. #define DEVICE_REG0 ((volatile unsigned long *) (0x40000000))   

2. #define DEVICE_REG0_BIT0 ((volatile unsigned long *) (0x42000000))   

3. #define DEVICE_REG0_BIT1 ((volatile unsigned long *) (0x42000004))   

4. *DEVICE_REG0_BIT1 = 0x1; // Set bit1 via bitband alias address  

At the same time, in GCC and RealView MDK (ie Keil) development tools, it is allowed to manually specify the address of a variable when defining it.

1. volatile unsigned long bbVarAry[7] __attribute__(( at(0x20003014) ));   

2. volatile unsigned long* const pbbaVar= (void*)(0x22000000+0x3014*8*4);  

3. pbbaVar[136]=1; //Set bit 136  

2.2 Embedded Flash

The structure diagram is as follows:

In the STM32F10xxx, the BOOT[1:0] pins can be used to select whether to boot the program from the main memory block, system memory or built-in SRAM.