Analysis of the Interface Between the Single Chip Microcomputer and IBM-PC Hard Drive Adapter

　　The 51 single-chip microcomputer has high integration, strong control and processing capabilities, and reliable and stable operation. It has been widely used in the fields of automatic detection of production processes, industrial real-time control, robots, communications, navigation, medical care, and intelligent instruments. In these applications, especially in the automatic testing and analysis of engineering signals, it is often necessary to record and store a large amount of data, and some data needs to be stored for a long time or permanently. At present, the tool for single-chip microcomputer systems to save and record data is random access memory (RAM). As we all know, RAM cannot save data for a long time. The maximum data storage capacity of the 51 series single-chip microcomputer system is only 64 KB, so these methods cannot meet the requirements of some practical systems. At present, magnetic recording technology is very mature, and hard disk recording and storage systems have become the mainstream equipment in computer systems. It has a large storage capacity, high access speed, can permanently save data, and the price is getting lower and lower. Applying it to the single-chip microcomputer system can greatly improve the performance of the system.
　　
　　IBM-PC computers support hard disk systems, and the interface technology between the host and the hard disk has been standardized and has been widely used. The hard disk system of IBM-PC is used as the data storage device of the 51 series single-chip computer system. The interface circuit structure is simple and there is no need to specially design a hard disk drive circuit. Therefore, the application system constructed has a very high performance-price ratio.

1. Design of interface circuit

　　IBM - PC hard disk drive adapter is called hard disk controller for short. It is an intelligent component that can connect one or two hard disks and is connected to the PC through the 62-pin I/O channel slot on the system board. Only 40 of the 62 signal lines are used here, of which AO~A19 are 20-bit address lines; DO~D7 are 8-bit data lines; MEMR is used for the basic I/O program of reading the hard disk; IOR and IOW are the control signals for the host to read and write the hard disk controller respectively; IRQ5 and DRQ3 are the interrupt request and DMA request signals of the hard disk controller respectively; DACK3 is the signal sent to the controller when the host responds to DMA; there is also a RESET signal to reset the hard disk controller, an AEN signal to prohibit I/O operations during DMA data transmission, and 6 power and ground lines. The host reads data from the hard disk or writes data to the hard disk by writing commands and control words to the 6 accessible registers provided by the hard disk controller. Therefore, when designing the interface circuit between the microcontroller and the hard disk controller, it is only necessary to consider the generation and reception of the above signals, the expansion of the microcontroller data storage, the connection of the DMA controller, and other issues. In a PC, the 6 accessible registers of the hard disk controller occupy the I/O port addresses 320-323H of the host. The sending and receiving of signals are addressed through these port addresses. Only 10 of the 20 address lines are actually used. The 51 series microcontroller has 16 address lines, which can meet the requirements of address decoding. The 51 series microcontroller does not directly support the DMA data transfer method, and the data between the hard disk controller and the data storage must use the DMA method. In a PC, the host's read/write operation on the hard disk controller is realized by reading/writing the I/0 port, and the microcontroller system does not have I/O read/write instructions. The memory mapping method can be used to map the 4 addresses of the hard disk controller to the external data storage, so that the controller's IOR and IOW are connected to the WR and RD of the microcontroller respectively. The interrupt request signal IRQ5 of the hard disk controller is only used for the hard disk operation end signal, so this signal is used as the INT1 of the microcontroller. The connection method of other signal lines is not repeated. This interface circuit is shown in Figure 1-91.

2. Software Design

　　In IBM-PC, the host can call the BIOS program to diagnose the controller, drive and hard disk, store and retrieve data, set hard disk parameters, test whether the hard disk drive is ready, format the hard disk, etc.; it can flexibly process and handle data files through the DOS interrupt program; it can also start and boot the system through the hard disk and install various applications. Therefore, its software structure is very complex and the program volume is also large. In this example, the hard disk is only used as a large-capacity data storage, so it only needs to simply format the disk, read/write data, and test the quality and readiness of the hard disk drive, etc., which can be achieved by writing commands and control words to the 6 registers of the controller. The access logic of these 6 registers is shown in Table 1-25.

　　The data input/output register (DIOR) is very important and is the main signal throughput port of the controller. The status register (321R) provides the hardware status of the hard disk controller. Figure 1-92 shows the function of each bit of this register. The functions and uses of the other four registers can be found in relevant literature and will not be repeated here. The command of the hard disk controller is a word block composed of 6 bytes, called a command block. 19 commands can be issued by the command block. This section only selects a few of them, such as read disk (READ), write disk (WRITE), format drive ( FM TDRV) and test whether the drive is ready (TSTRDY). The entire execution process of a hard disk controller command can be divided into three stages: command sending, execution and end. In the command sending stage, the "select controller" register must be written first to "start" the hard disk controller, and then a 6-byte command block is written to the controller; in the command execution stage, the controller performs various operations according to the received command content; when the command is executed, the whole process of command execution is completed only when the host reads the "completion status" byte through DIOR, otherwise, the working state of the hard disk controller will be chaotic. The "completion status" byte provided by the controller is mainly to report to the host whether an error occurs in this operation. If an error occurs, the host can also read out the type of error, the sector address of the error, and other information.

　　According to the above analysis, the software design is as follows:
　　
　　(1) Main monitoring program
　　
　　This part of the program mainly implements the initialization and parameter setting functions of the hard disk controller. Its program flowchart is shown in Figure 1-93.
　　
　　(2) Functional module
　　
　　For the reading/writing of data on the hard disk, the controller adopts the DMA data transmission method. When the data reading/writing operation is completed, the controller also sends an interrupt request signal to report that the command execution is completed. Therefore, for the disk reading and writing operations, after entering the functional program, first set the parameters and working status of the DMA controller, initialize the interrupt service program; then write the command block and DMA, interrupt enable, and enter the read/write operation. The write disk program flow chart is shown in Figure 1-94.

　　The disk read operation is very similar to the disk write operation, except that the data transfer direction is opposite. Therefore, the program structure is basically the same and will not be repeated here.
　　
　　Operations such as testing whether the hard disk is ready and formatting the hard disk do not require data transmission. This part of the program does not require DMA participation, but hardware interrupts are still required. Other operations are basically the same as the disk write operation and will not be explained. The
　　
　　interface circuit between the 51 single-chip microcomputer and the IBM-PC hard disk drive studied in this case has been applied to portable intelligent data analysis and testers, with stable and reliable performance. Since the way data is stored on the hard disk is the same as that of the IBM-PC, the single-chip microcomputer system can share data with the IBM-PC, which provides great convenience for engineering and technical personnel.