Analysis of 5 interrupt sources of 8051 microcontroller

    When several interrupt sources request an interrupt to the CPU at the same time, they are queued according to the severity of the real-time events that occur, and the interrupt request of the most urgent event is processed first. Therefore, the single-chip microcomputer specifies the priority level of each interrupt source.
　　
　　When the CPU is processing an interrupt request, another interrupt request with a higher priority occurs. The CPU temporarily suspends the processing of the previous interrupt and turns to process the interrupt request with a higher priority. After processing, it continues to execute the original interrupt processing program. This process is called interrupt nesting, and such an interrupt system is called a multi-level interrupt system.
　　
　　Since the program that the CPU is executing is randomly interrupted by an external asynchronous event, when the CPU turns to execute the interrupt service program, in addition to the hardware automatically pushing the power-off address, that is, the value of the 16-bit PC program counter into the stack, the user must also pay attention to protecting the relevant working registers, accumulators, flags, etc. This process is usually called protecting the scene. In order to restore the contents of the original working registers, accumulators, flags, etc. after completing the interrupt service program, this process is called restoring the scene; finally, the interrupt return instruction is executed, the power-off is automatically popped out to the PC, and the main program is returned to continue executing the interrupted program.
　　
　　Next, let's look at the 8051 interrupt system structure and interrupt control:
　　
　　The 8051 microcontroller has five interrupt request sources and four registers for interrupt control, IE.IP.TCON and SCON, which are used to control the type of interrupt, interrupt enable, interrupt start and stop, and the priority level of various interrupt sources.
　　
　　The five interrupt sources have two priorities, and each interrupt source can be programmed as a high priority or low priority interrupt, which can achieve two-level interrupt service program nesting. The interrupt sources of 8051 include: external interrupt sources input from the INT0 and INT1 pins; three internal interrupt sources, namely the overflow interrupt source of timer T0, the overflow interrupt source of timer T1, and the send/receive interrupt source of the serial port. The
　　
　　two external interrupt sources input from the INT0 and INT1 pins and their trigger mode control bits are latched in the lower four bits of the special function register TCON, and the format is as follows:

IE1, i.e. TCON.3: External interrupt INT1 request flag. When the CPU detects an external interrupt signal on the INT1 pin, the hardware sets IE1=1 to request an interrupt. After the CPU executes the interrupt service program, the IE1 bit is automatically cleared by the hardware.
　　
　　IT1, i.e. TCON.2: External interrupt INT1 request type, trigger mode control bit, set to 1 or cleared to 0 by software to control the trigger type of external interrupt 1.
　　
　　IT1=0, external interrupt 1 is set to level trigger mode. When the pin INT1 inputs a low level, IE1 is set to request an interrupt. The CPU samples the input level of INT1 during S5P2 of each machine cycle . When the low level is sampled, IE1=1 is set. When the level trigger mode is used, the external interrupt source input to the pin INT1 must maintain a valid level until the program is responded to by the CPU. At the same time, before the interrupt service program is executed, the valid level of the external interrupt source must be revoked, otherwise another interrupt will be generated.
　　
　　IT1=1, external interrupt 1 is set to edge trigger mode, and the CPU samples the level of the pin INT1 in each machine cycle. If in two consecutive samplings, the pin INT1 is sampled as high level in one cycle, and then the pin INT1 is sampled as low level in the next cycle, INE1 is automatically cleared to 0 by hardware. Because the external interrupt input level is sampled once per machine cycle, the high and low level time of the external interrupt source input must be maintained for more than 12 oscillation cycles to ensure that the CPU detects the negative jump signal, that is, the falling edge.
　　
　　IEO, i.e. TCON.1: External interrupt request flag. When IE0=1, external interrupt 0 requests an interrupt from the CPU. When the CPU responds to the external interrupt, IE0 is cleared to 0 by hardware.
　　
　　ITO, i.e. TCON.0: External interrupt 0 trigger mode control bit. IT0=0, external interrupt 0 is set to edge trigger mode. When IT0=1, external interrupt 0 is set to edge level trigger mode. Its function is similar to IT1.
　　
　　Interrupt control: In addition to some bits in the special function registers TCON and SCON that are related to interrupts, there are two special function registers IE and IP specifically used for interrupt control.
　　
　　Interrupt enable IE:

In the 8051 microcontroller, the special function register IE is the interrupt enable register, which controls whether the CPU allows or prohibits interrupt sources in general and whether each interrupt source allows interrupts. Its format is:
　　
　　EA: interrupt enable bit. EA=1, CPU allows interrupts; EA=0, CPU prohibits all interrupt requests.
　　
　　ES: serial interrupt enable bit. ES=1, serial port interrupts are allowed; ES=0, serial port interrupts are prohibited.
　　
　　EX1: T0 overflow interrupt enable bit. ET0=1, T0 interrupt is allowed; ET0=0, T0 interrupt is prohibited.
　　
　　EX0: external interrupt enable bit. EX0=1, external interrupt 0 interrupt is allowed; EX0=0, external interrupt 0 interrupt is prohibited.
　　
　　After the 8051 system is reset, all bits in IE are cleared to 0, that is, all interrupts are prohibited.
　　
　　Interrupt priority setting register IP. The 8051 microcontroller has two interrupt priorities. Each interrupt source can be programmed as a high priority interrupt or a low priority interrupt, and two-level interrupt nesting can be realized. A high priority interrupt source can interrupt the low priority interrupt service program being executed.
　　
　　Interrupt sources of the same or lower priority cannot interrupt the interrupt program being executed. For this reason, in the 8051 interrupt system, there are two priority status triggers inside , which indicate whether the CPU is executing a high priority or low priority interrupt service program, thereby respectively shielding all interrupt requests and other interrupt source requests of the same level.
　　
　　The special function register IP is the interrupt priority register.

    The control bit of each interrupt source priority can be set by the user through software. Its format is as follows:
　　
　　PS: Serial interrupt priority control bit. PS=1, set the serial port as a high priority interrupt; PS=0, low priority.
　　
　　PT1: T1 interrupt priority control bit. PT1=1, set timer T1 as a high priority interrupt; PT=0, low priority.
　　
　　TX1: External interrupt 1 interrupt priority control bit. PX1=1 sets external interrupt 1 as a high priority interrupt; PC1=0, low priority.
　　
　　PT1: T1 interrupt priority control bit. PT1=1, set timer T1 as a high priority interrupt; PT1=0, low priority.
　　
　　PT0: T0 interrupt priority control bit. PT1=1, set timer T0 as a high priority interrupt; PT0=0, low priority.
　　
　　PX0: External interrupt interrupt priority control bit. PX0=1, set INT1 as a high priority. PX0=0, low priority.
　　
　　After the 8051 is reset, the lower five bits of IP are all cleared to 0, and all interrupt sources are set to low priority interrupts.
　　
　　If several interrupt sources of the same priority level request interrupts from the CPU at the same time, which one gets serviced depends on the order in which they are registered in the CPU. The CPU queries the registration number through internal hardware and decides which interrupt request to respond to first according to the natural priority. The natural priority is in the following order from high to low: external interrupt 0, timer 0, external interrupt 1, timer 1, serial interrupt.