Design of Interface between NOR Flash and 8-bit MCU

　　introduction

　　Flash memory, also known as flash memory, is a new type of semiconductor non-volatile memory that gradually developed in the late 1980s. It has the characteristics of both RAM and ROM, and can be erased and rewritten online, and can keep data from being lost after power failure.

　　NOR Flash is the earliest type of Flash memory. Compared with other types of Flash memory, it has the following advantages: high reliability, fast random read speed, single-byte or single-word programming, allowing the CPU to read code directly from the chip for execution, etc. Therefore, NOR Flash memory occupies a very important position in the application development of embedded systems. This article takes SST's NOR Flash chip SST39SF040 and MCS-51 microcontroller as examples, and introduces the design methods of its interface hardware and interface software in detail, focusing on the particularity of the application of large-capacity NOR Flash in 8-bit low-end microcontrollers.

　　1 SST39SF040 chip introduction

　　SST39SF040 is a NOR Flash memory based on SuperFlash technology recently launched by SST. It belongs to SST's parallel flash memory series. It is suitable for occasions that require online program writing or large-capacity, non-volatile data repeated storage.

　　1.1 Chip internal functional structure and external pins

　　Figure 1 is the internal functional structure block diagram of SST39SF040, which consists of Super-Flash storage unit, row decoder, column decoder, address buffer and latch, input/output buffer and data latch, control logic circuit, etc. Figure 2 is its external pin distribution diagram, where A18~A0 are address lines, CE is the chip selection signal, OE can be used as a read signal, WE is a write signal, and DQ7~DQ0 are data lines.

　　1.2 Main features of the chip

　　① The capacity is 512KB, organized in a 512K×8-bit structure.

　　② It adopts a single 5V power supply, and the programming power supply VPP is generated inside the chip.

　　③ The chip can be erased and written repeatedly 100,000 times, and the data can be retained for 100 years.

　　④ The typical value of the working current is 10mA, and the typical value of the standby current is 30μA.

　　⑤ Sector structure: The sector size is uniformly 4KB.

　　⑥ Typical values ​​of read, erase and byte programming time: data read time is 45~70ns; sector erase time is 18ms, whole chip erase time is 70ms; byte programming time is 14μs.

　　⑦ There is a status flag to record whether the internal erase operation and programming operation are completed.

　　⑧ It has hardware and software data protection functions.

　　⑨ Has address and data latch function.

　　1.3 Chip Operation

　　1.3.1 Chip software operation command sequence

　　The software operations of SST39SF040 can be divided into two categories: normal read operations and command operations.

　　The normal read operation is very simple, similar to the RAM read operation. When the OE and CE signals are both low, data can be read from the chip.

　　The command operation of the chip includes chip identification, byte programming, sector erasing, and whole chip erasing. These operations are completed by their respective software operation command sequences, as listed in Table 1. Among them, BA is the address of the byte to be programmed, Data is the byte programming data, and SAX is the address of the sector to be erased. Only the lower 15 bits of the address in the command are valid, and the upper 4 bits can be set to "0" or "1" arbitrarily.

　　The software operation command sequence of SST39SF040 is actually composed of one or more bus write operations. Taking the sector erase of SST39SF040 as an example, its operation process includes three steps: Step 1, start the erase mode, which is implemented by the bus write operation of the 1st to 5th cycle given in Table 1; Step 2, load the sector erase command (30H) and the address of the sector to be erased, which is implemented by the corresponding bus write operation of the 6th cycle; Step 3, perform internal erase. The maximum internal erase time is 25ms.

　　When the bus is written, OE must be kept at a high level, and CE and WE should be at a low level. The latching of address and data is controlled by the edges of the CE and WE signals. The falling edge that appears later will latch the address, and the rising edge that appears earlier will latch the data.

　　1.3.2 Status Detection of Byte Program and Erase Operations

　　It takes a certain amount of time for the chip to perform internal byte programming or erasing operations. Although a fixed delay can be used to wait for the completion of these operations, in order to optimize the system's byte programming and erasing operation time and to timely determine whether the internal operation is completed, SST39SF040 provides two status bits for detection, namely the jump bit DQ6 and the data query bit DQ7. When the chip is performing internal operations, as long as DQ6 or DQ7 is queried according to the process of Figure 3, a judgment can be made in time.

　　2 Interface design between SST39SF040 and MCS-51

　　2.1 Hardware Design

　　Hardware design is to build a suitable interface circuit to connect SST39SF040 to the system bus of MCS-51. According to the structural characteristics of SST39SF040 and MCS-51 series microcontrollers, we found that the data line and read and write signal lines of SST39SF040 can be easily connected to the system bus of MCS-51, so the main issue to consider is the connection of SST39SF040 address line. Since its capacity has exceeded the addressing range of MCS-51, 19 address lines cannot be connected to the address bus of MCS-51, so further memory expansion must be carried out in this system. Memory expansion can usually be achieved by using the idle I/O port lines of the microcontroller as page address output pins. However, in many application systems, the I/O port lines of the microcontroller are very tight. When there are no extra I/O port lines, the page address must be output from the data bus in advance and stored in the latch for standby. The specific method is: hang the latch directly on the data bus, arrange an I/O address for it, so as to form a page register. When accessing the memory, write the page address as data into the page register in advance.

　　According to the above analysis, the interface circuit between SST39SF040 and MCS-51 can be designed, as shown in Figure 4. In this system, the 512 KB memory is divided into 32 pages, each page size is 16 KB. It can be obtained that the page address requires 5 bits and the page offset requires 14 bits. The page address is given before the memory access. The specific method is: use a "MOVX" command to output the page address to the latch 74LS374, and then the 74LS374 keeps the page address on the address pins A14~A18 of the memory. The page offset is directly given in the read and write commands of the memory. When executing the command, the lower 8-bit address A0~A7 is output from the P0 port to the 74LS373 for retention; the address A8~A13 is directly provided by the P2.0~P2.5 of the microcontroller. The address signals A0~A18 outputted in the above time-sharing mode will be effective at the same time after the read/write control signal starts to work, so as to realize the access to the 512KB full address space of SST39SF040. P2.6 and P2.7 are used as chip select signals of SKT39SF040 and latch 74LS374 respectively. The chip select signal address range of SST39SF040 is 8000H~BFFFH, and the chip select signal address range of 74LS374 is 4000H~7FFFH.

　　2.2 Software Design

　　Software design is to write the operating procedures for SST39SF040, including byte reading, sector or whole chip erasing, and byte programming. The following is the erase procedure for the first sector, where DELAY25 is a 25ms delay subroutine. Other operating procedures can be written with reference to this.

　　The difficulty in the program writing process is how to decompose the unit address to be accessed in SST39SF040 and correspond it to the read and write commands. Taking the first command of the sector erase operation as an example, the function of this command is to write data AAH to address 5555H. For address 5555H, its highest 5 bits A18~A14 are 01H, and the lower 14 bits A13~A0 are 1555H. The page number determined by the highest 5 bits of the address must first be written into the latch 74LS374 as data, and then the data AAH is written into the unit determined by the lower 14 bits of the address in the page. When writing the page number, the address in the instruction can be selected from the range of 4000H~7FFFH, that is, the latch 74LS374 is selected; when writing data AAH, the address in the instruction can be obtained by adding 8000H to the lower 14 bits of the address 1555H, and its value is 9555H.

　　Conclusion

　　This paper analyzes and discusses the interface technology between large-capacity NORFlash memory and 8-bit microcontroller from both hardware and software aspects, and gives a specific design scheme. Its ideas and methods have a high reference value for the application design of embedded systems. The author has applied it to the design and development of an attendance machine product.