Basic knowledge of overall analysis of the running process of ucos on s3c2410

User mode (user mode), the normal mode for running applications;

Fast interrupt mode (fiq mode) is used to support data transmission or channel processing;

Interrupt mode (irq mode), used for normal interrupt processing.

Super user mode (svc mode), the protected mode of the operating system

Abnormal interrupt mode (abt mode), enter or pre-fetch abnormal interrupt instructions after entering data

System mode (sys mode) is a privileged user mode used by the operating system

Undefined mode (und mode), which is entered when an undefined instruction is executed

External interrupts, abnormal operations or software control can change the interrupt mode. Most applications run in user mode. Entering privileged mode is to handle interrupt or abnormal requests or operate protection resource services.

These working modes are different environments for programs to run provided by chip hardware. Different modes have different hardware access permissions and use different registers. This provides different permission mechanisms for different programs. For example, your operating system code runs in a mode with higher permissions, while your application runs in a mode with lower permissions. This protects the operating system code.

Registers, registers visible in each mode and the functions of each register:

ARM has a total of 37 32-bit registers, 31 of which are general registers and 6 are status registers. But at the same time,

Not all registers are visible to the programmer. Whether a memory is visible (accessible) at a certain moment is a function of the

The registers in each mode are shown in Figure 1:

The registers used in system mode and user mode are the same. The registers shaded with triangles represent the registers used in different modes.

There are different physical registers.

The following is a classification description:

General registers

ARM's general registers include R0~R15, of which R0~R7 are ungrouped registers and use the same registers in all modes.

R8~R14 are independent physical registers in FIQ mode, the purpose of which is to speed up the interrupt response speed.

Save the program execution scene. R13 and R14 have their own independent registers in each mode. R15 has only

One, common to all modes.

The following is an introduction to the special functions of these registers:

Register R13: In ARM instructions, R13 is often used as a stack pointer. Each operating mode has its own independent stack, which is used to save the program running environment when an interrupt occurs and to perform process control when the C language is executed.

Register R14: Dedicated to holding the return point address, when the system executes a "jump and link" (BL) instruction

, R14 will receive a copy of R15. Otherwise, it can be used as a general-purpose register.

In other modes, the private registers R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are also used to save

When an interrupt or exception occurs, or when a BL instruction is executed during an interrupt or exception, the return value of R15.

Register R15 is the program counter (PC). In ARM state, bits [1:0] of R15 are 0, and bits [31:2] store the PC.

In Thumb state, bits[0] is 0 and bits[31:1] store the PC value.

FIQ mode has 7 private registers R8-14 (R8_fiq-R14_fiq). In ARM state, most FIQ processing does not need to save any registers. User, Interrupt, Abort, Supervisor and Undefined modes have 2 private registers, R13 and R14. These modes are allowed to have a private stack pointer and link register.

Program Status Register

ARM920T has a current program status register (CPSR) and 5 saved program status registers (SPSRs) for exception interrupt processing. The functions of these registers are:

Keep information about the most recently completed ALU operation;

Control the enabling and disabling of interrupts;

Sets the operating mode of the processor.

Figure 2 below shows the bit definition of the program status register:

For the specific meaning of these bits, seethe detailed explanation of the ARM920T interrupt system . That’s all about the ARM chip knowledge related to UCOS. Of course, there is a lot more ARM chip knowledge to learn. Please refer to the 920T datasheet! ! ! !