S3C2440 Interrupt Analysis

A few days ago, I basically got the external interrupt working, but I didn't know much about the specific meaning and difference of several interrupt registers. Today, I read the datasheet in detail and searched for relevant information on the Internet. The results are recorded as follows:

The interrupt register of S3C2440 has 6 interrupt arbitrators, which are divided into 2 levels: 5 in the first level and 1 in the second level. For details, see interrupt sources P380 and interrupt sub sources P381 in the datasheet. The 32 interrupt sources in the first level include 26 internal interrupts and 6 external interrupts.

These 6 interrupts are: EINT0, EINT1.EINT2, EINT3, EINT4_7, EINT8_23. Among them, EINT4_7 and EINT8_23 share one interrupt. When there is an interrupt request from an external interrupt, because EINT4_7 and EINT8_23 share interrupts respectively, and BIT4 or BIT5 of SRCPND and INTPND are also shared, how to distinguish whether it is EINT4, EINT5 or EINT6 that has an interrupt? This requires another register EINTPEND to judge. Since EINT0~EINT3 each share one interrupt, EINTPEND only has EINT4~23. Reading this register will tell you which interrupt has been triggered.

1. Three interrupt pending registers: source pending register SRCPND, interrupt pending register INTPND and external interrupt pending register EINTPEND.

The effective bit of the SRCPND register is 32 bits, and each bit corresponds to an interrupt source. When a bit is set to 1, it means that the corresponding interrupt is triggered. However, we know that the system can trigger multiple interrupts at the same time. As long as the interrupt is triggered, the corresponding bit is set to 1 until the bit is cleared. That is to say, multiple bits of the SRCPND register can be set to 1 at the same time. This bit is cleared to 0 after writing 1.

The effective bits of the INTPND register are 32 bits, which seems to be the same as SRCPND, but in fact, there is a big difference. At a certain moment, only one bit of the INTPND register can be set to 1. If a bit of INTPND is set to 1, it means that the interrupt corresponding to this bit has the highest interrupt priority among all the triggered interrupts and is not masked, indicating that the CPU is about to or is already processing the interrupt corresponding to this bit. This bit is cleared to 0 after writing 1.

The difference between the two: SRCPND indicates what interrupt is currently triggered; INTPND indicates that the CPU is about to or is processing an interrupt.

EINTPEND: The register has 24 valid bits, and the lower 4 bits are reserved. EINTPENG has only EINT4~E23. Like SRCPND, multiple bits can be 1 at the same time. It is used to distinguish which of the shared interrupts EINT4_7 and EINT8_23 triggered it. This bit is cleared to 0 after writing 1.

For example, in the interrupt handler of the external interrupt routine, it is written as follows:
                        if(rINTPND==0x10)

                       {

                                     rSRCPND = 0x10;

                                     rINTPND = 0x10;
                                     if(EINTPEND & 0X10) //EINT4
                                     {
                                               EINTPENG |= 0X10;
                                               Uart_Printf("K4 interrupt occurs\n");
                                     }

                                      if(rEINTPEND&0x20) //EINT5

                                     {

                                                rEINTPEND |= 0x20;

                                                Uart_Printf("K5 interruption occurred\n");                                                                     

                                       }

                       The judgment condition is INTPND .
If the INTPND bit is set to 1, it means that the current CPU is processing EINT4_7. Write 1 to both bit 1 of SRCPND and INTPND to clear the flag. if(EINTPEND & 0X10) is the second judgment condition, confirming that the EINT4 in EINT4_7 has an interrupt.

2. INTMOD interrupt mode register, each bit corresponds to each bit in SRCPND. 0--IRQ mode, 1--FIQ mode, default initialization all 0.

Only one interrupt source can be set to FIQ at a time, so only one position in INTMOD can be set to 1 at a time. FIQ interrupt priority is higher than IRQ.

3. INTMSK interrupt mask register, each bit corresponds to each bit in SRCPND. 0--unmasked, 1--masked interrupt request, default initialization all 1.

4. INTSUBMSK and SUBSRCPND are the secondary interrupt source pin registers, and their usage is similar to the primary interrupt source. The second-level secondary interrupt source list is in datasheet P381.