S3C2410 interrupt handling

    Before introducing the interrupt handling of 2410, we have to take a look at the ARM exception vector table (Exception Vectors). Here is a brief introduction to the exception vector table (Exception Vectors):

    The ARM exception vector table is generally stored at 0x00000000. ARM920T can handle 7 exceptions: Reset, Undefined instruction, Software Interrupt, Abort (prefetch), Abort (data), IRQ, FIQ

The following is a snippet of the system source code:

    The above snippet usually appears in an assembly file called "head.s". The statement "b Handle_Reset" is the first statement to be executed after the system is powered on, because after powering on, the CPU will fetch the first instruction from 0x00000000 of SDRAM and execute it.

     After the system is powered on, the CPU will fetch the first instruction from the SDRAM address 0x00000000 and execute it. The terminal vector table will be placed at the address 0x00000000 as shown above. Whenever an exception occurs in the system, the CPU will check the interrupt vector table from the memory address 0x00000000 according to the exception number and perform corresponding processing. For example, if the system triggers an IRQ exception, and IRQ is exception number 6, the CPU will point the PC to the address 0x00000000 and call the interrupt service program.

    The S3C2410 chip can receive 56 interrupt sources and generate 32 interrupt requests. These interrupt sources come from two parts: internal peripherals, such as DMA controller, UART, etc. and external pin lines. ARM920T has two types of interrupt modes: FIQ and IRQ, and generates IRQ or FIQ interrupts by determining the priority. If the control bit F position of the PSR (Program Status Register) in the CUP of ARM920T is 1, the CPU does not accept FIQ interrupts from the interrupt controller. If the control bit I position of the PSR (Program Status Register) in the CUP of ARM920T is 1, the CPU does not accept IRQ interrupts from the interrupt controller, so the interrupt controller generates an interrupt by clearing the F-bit or I-bit.

      The interrupt exception handling module of S3C2410 consists of the following registers:

•  SRCPND,

• INTMODE,

• INTMSK,

• PRIORITY,

• INTPND,

• INTOFFSET,

• SUBSRCPND,

• INTSUBMSK.

The functions of each register are described in detail below: 

      The SRCPND (Source Pending Register) register has 32 valid bits, which can be read and written. Each bit involves an interrupt source. SRCPND is the main interrupt source pin register. A bit set to 1 indicates that the corresponding interrupt is triggered. However, we know that the system can trigger several interrupts at the same time. As long as the interrupt is triggered, the corresponding bit of SRCPND will be set to 1, which means that several bits of SRCPND can be set to 1 at the same time. In addition, this register is not affected by the priority logic of the interrupt controller. If this interrupt is not masked by the INTMSK register or is a fast interrupt (FIQ), it will be further processed. The corresponding bit of SPCPND can be cleared by writing data to this register.

      The effective bits of the INTMODE (Interrupt Mode Register) register are 32 bits, which can be read and written. Each bit corresponds to each bit in SRCPND. Its function is to specify the interrupt source processing mode (IRQ or FIQ) corresponding to the bit. If a bit is 0, the interrupt corresponding to the bit is processed in IRQ mode, and if it is 1, it is processed in FIQ mode. The initialization value of this register is 0x00000000, that is, all interrupts are processed in IRQ mode. There is only one interrupt source in this interrupt controller that can use FIQ mode (use FIQ mode under emergency interrupt), so only one bit of INTMODE can be set to 1.

     The effective bit of INTMSK (Interrupt Mask Register) register is 32 bits, which can be read and written. INTMSK is the main interrupt mask register corresponding to the SRCPND register. Its function is to determine whether the interrupt request corresponding to this bit is processed. If a bit is set to 1, the interrupt corresponding to this bit will be ignored after it is generated (the CPU does not process the interrupt request). If it is set to 0, the CPU processes it. The initialization value of this register is 0xFFFFFFFF, that is, all interrupts are masked by default.

      The PRIORITY (IRQ PRIORITY Control Register) register has 32 bits, with valid bits [20:0], which can be read and written. The function of this register is that if several interrupt sources are triggered at the same time, according to the flow of Figure 2.2.1, if these interrupt sources are not blocked and are all in IRQ mode, it is necessary to determine which interrupt source has the highest priority, so that its corresponding position in the INTPND register is 1, and the CPU turns to the corresponding interrupt service program to let the interrupt service program handle the corresponding interrupt request.

      The effective bits of the INTPND (Interrupt Pending Register) register are 32 bits, readable and writable. It looks the same as the SRCPND register, but they actually have significant differences in function. Only one bit can be set to 1 at a time. If a bit of INTPND is set to 1 (the interrupt corresponding to this bit has the highest priority among all the interrupts that have been triggered and the interrupt is not masked), it means that the CPU is about to or has already processed the interrupt corresponding to this bit. Therefore, the SRCPND register indicates what interrupt has been triggered, while the INTPND register indicates that the CPU is about to or has already processed a certain interrupt.

      The valid bits of INTOFFSET (Interrupt Offset Register) register are 32 bits and read-only. The value of this register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be automatically cleared by clearing SRCPND and INTPND. FIQ mode interrupts will not affect the INTOFFSET register, so this register is only valid for IRQ mode interrupts.

      The SUBSRCPND (Sub Source Pending Register) register has 32 bits, with valid bits [10:0], which are readable and writable. Each bit represents an interrupt source. SRCPND is the main interrupt source pin register, and it is the sub interrupt source pin register, which is similar to SRCPND.

      The INTSUBMSK (Interrupt Sub Mask Register) register has 32 bits but the effective bits are 11 bits, which is readable and writable. If the mask bit is 0, this interrupt request is serviced, similar to INTMSK.