// Chip ATMEGA16L
// Clock 4MHz internal
// Use system built-in delay program
#include
#include
#define SCLK5615 PORTD.4 // tlc5615 clock line, PD4 output
#define DATA5615 PORTD.5 // tlc5615 data line, PD5 output
#define CS5615 PORTD.6 // tlc5615 chip select line, PD6 output
void tlc5615(unsigned int dat);
void main()
{
delay_ms(200);
DDRD=0xff;
tlc5615(200); // Conversion output voltage = 2*Vref*code/1024, the maximum output voltage is the power supply voltage. The current output is 1.77V.
while(1);
}
void tlc5615(unsigned int dat)
{
unsigned char i;
CS5615=1;
DATA5615=0;
SCLK5615=0; // During CS high level, SCLK is low level
dat<<=6; // Shift the digital quantity dat left by 6 bits, and keep the lower 10 bits of the original dat. The upper 10 bits of the new dat are valid, and the lower 6 bits are all 0.
CS5615=0; // CS chip select is valid, start receiving data
SCLK5615=0;
for(i=0;i<12;i++) // Send 10 bits of data and 2 bits of 0, starting from the highest bit.
{ // Non-cascade mode, only 12 bits of data need to be input.
if((dat&0x8000)==0x8000)
DATA5615=1;
else
DATA5615=0;
SCLK5615=1; // SCLK rising edge, data input
dat<<=1;
SCLK5615=0; // SCLK returns to low level
}
CS5615=1; // CS rising edge, data sent to DAC register
// The rising and falling edges of CS are only valid when SCLK is low
SCLK5615=0;
DATA5615=0; // Pull up the chip select end, pull down the clock end and data end, and return to the initial state
}
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