STM32 GPIO port output: open drain output and push-pull output

>>Push-pull output: can output high and low levels, connect digital devices

>>Open-drain output: The output terminal is equivalent to the collector of the transistor. A pull-up resistor is required to obtain a high-level state. It is suitable for current-type driving and has a relatively strong ability to absorb current (generally within 20ma).

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Short answer:
1. Some 3.3V devices are 5V compatible and can be directly connected using this capacitance.
2. Use voltage conversion devices, such as TPS76733, which converts 5V input into 3.3V, 1A output.
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Open-drain circuit characteristics and applications

When designing circuits, we often encounter the concepts of open drain and open collector. The "drain" mentioned in the concept of open drain circuit refers to the drain of MOSFET. Similarly, the "collector" in the open collector circuit refers to the collector of the transistor. An open drain circuit refers to a circuit with the drain of MOSFET as the output. The general usage is to add a pull-up resistor to the circuit outside the drain. A complete open drain circuit should consist of an open drain device and an open drain pull-up resistor.

The circuits that form the open-drain form have the following characteristics:
1. Utilize the driving capability of the external circuit to reduce the internal driving of the IC. When the internal MOSFET of the IC is turned on, the driving current flows from the external VCC through R pull-up, MOSFET to GND. Only a very low gate driving current is required inside the IC. As shown in Figure 1.
2. Multiple open-drain output pins can be connected to one line. Form an "AND logic" relationship. As shown in Figure 1, when any one of PIN_A, PIN_B, and PIN_C becomes low, the logic on the open-drain line is 0. This is also the principle of I2C, SMBus and other buses to determine the bus occupancy status.
3. The transmission level can be changed by changing the voltage of the pull-up power supply. As shown in Figure 2, the logic level of the IC is determined by the power supply Vcc1, and the output high level is determined by Vcc2. In this way, we can use low-level logic to control the output high-level logic.
4. If the open-drain pin is not connected to an external pull-up resistor, it can only output a low level (therefore, for the P0 port of the classic 51 single-chip microcomputer, an external pull-up resistor must be added if it wants to have input and output functions, otherwise it cannot output high-level logic).
5. The standard open-drain pin generally only has output capabilities. Adding other judgment circuits can have the ability of bidirectional input and output.

Notes in application:
1. The principles of open drain and open collector are similar. In many applications, we use open collector circuits instead of open drain circuits. For example, an input pin is required to be driven by an open drain circuit. Then our common driving method is to use a transistor to form an open collector circuit to drive it, which is convenient and cost-saving. As shown in Figure 3.
2. The resistance value of the pull-up resistor R pull-up determines the speed of the edge of the logic level conversion. The larger the resistance value, the lower the speed and the lower the power consumption. Vice versa.

Push-Pull output is generally called push-pull output. It should be more suitable than CMOS output in CMOS circuits because the push-pull output capacity in CMOS cannot be as large as bipolar. The output capacity depends on the area of ​​the N-tube and P-tube of the internal output electrode of the IC. Compared with open-drain output, the high and low levels of push-pull are determined by the power supply of the IC, and simple logic operations cannot be performed. Push-pull is the most commonly used output stage design method in CMOS circuits.
Attention when simulating I2C interface of at91rm9200 GPIO! !

1. What are OC and OD

Open-drain gate (open collector OC or open source OD)
Open-drain means open-drain output, which is equivalent to open-collector output, that is, open-collector (OC) output in TTL. It is generally used for line or, line and, and some are used for current drive.
Open-drain refers to MOS tubes, and open-collector refers to bipolar tubes. There is no difference in usage.
The circuit of open-drain form has the following characteristics:
1. Use the driving ability of the external circuit to reduce the internal drive of the IC. Or drive a load higher than the chip power supply voltage.
2. Multiple open-drain output pins can be connected to one line. Through a pull-up resistor, without adding any devices, a "and logic" relationship is formed. This is also the principle of I2C, SMBus and other buses to determine the bus occupancy status. If it is used as a totem output, a pull-up resistor must be connected. When connected to a capacitive load, the falling delay is the transistor in the chip, which is actively driven and has a faster speed; the rising delay is a passive external resistor with a slow speed. If high speed is required, the resistance should be small, and the power consumption will be large. Therefore, the selection of load resistance should take into account both power consumption and speed.
3. The transmission level can be changed by changing the voltage of the pull-up power supply. For example, adding a pull-up resistor can provide TTL/CMOS level output, etc.
4. If the open-drain pin is not connected to an external pull-up resistor, it can only output a low level. Generally speaking, open drain is used to connect devices of different levels and match the levels.
5. The normal CMOS output stage is an upper and lower tube. Removing the upper tube is OPEN-DRAIN. There are two main purposes of this output: level conversion and line AND.

6. Since the drain is open, the subsequent circuit must be connected to a pull-up resistor. The power supply voltage of the pull-up resistor can determine the output level. In this way, you can perform arbitrary level conversion.
7. The line-and function is mainly used in situations where multiple circuits pull down the same signal. If this circuit does not want to pull down, it will output a high level. Because the tube on the OPEN-DRAIN is removed, the high level is achieved by an external pull-up resistor. (For a normal CMOS output stage, if one output is high and the other is low, it is equivalent to a power short circuit.)

8. OPEN-DRAIN provides a flexible output mode, but it also has its weakness, which is the delay of the rising edge. Because the rising edge charges the load through an external pull-up passive resistor, when the resistor is small, the delay is small, but the power consumption is large; on the contrary, the delay is large and the power consumption is small. Therefore, if there is a requirement for delay, it is recommended to use the falling edge output.

2. What is Line-OR logic and Line-AND logic?

On a node (line), connect a pull-up resistor to the power supply VCC or VDD and the collector C or drain D of n NPN or NMOS transistors. The emitters E or sources S of these transistors are connected to the ground line. As long as one transistor is saturated, the node (line) will be pulled to the ground level.
Because the base of these transistors injects current (NPN) or the gate adds a high level (NMOS), the transistor will be saturated, so the relationship between these bases or gates to this node (line) is NOR logic. If an inverter is added after this node, it is OR logic.

Note: My personal understanding: Line AND, connect the pull-up resistor to the power supply. (~A)&(~B)=~(A+B), the origin of the concept of line AND is easier to understand from the formula;

If you use a pull-down resistor and a PNP or PMOS tube, you can form NAND logic, or use negative logic to convert AND/OR logic.

Note: Linear OR, connect the pull-down resistor to ground. (~A)+(~B)=~(AB);
These transistors are often the collector open circuit OC or source open circuit OD output terminals of some logic circuits. This logic is usually called line AND/line OR logic. When you see the OC or OD output terminals of some chips connected together and there is a pull-up resistor, this is line OR/line AND, but sometimes the pull-up resistor is built into the input terminal of the chip.
By the way, if it is not OC or OD, the output terminals of the chip cannot be connected together. The bidirectional output terminals on the bus BUS are connected together and are managed. Only one can be used as an output at the same time, while the others are in high impedance and can only be used as input.

3. What is a push-pull structure
? Generally, it refers to two transistors being controlled by two complementary signals, and one transistor is always turned on while the other is turned off. To realize line-and, an OC (open collector) gate circuit is required. If there are two transistors in the output stage, one is always turned on and the other is turned off, that is, the two transistors are connected in a push-pull manner. This circuit structure is called a push-pull circuit or a totem-pole output circuit (unfortunately, the picture cannot be posted). When the output is low, that is, when the lower load gate inputs a low level, the current at the output end will be the lower gate injected into T4; when the output is high, that is, when the lower load gate inputs a high level, the current at the output end will be the lower gate pulled out from the current power supply through T3 and D1. In this way, when the output is high or low, T3 and T4 will work alternately, thereby reducing power consumption and improving the tolerance of each tube. In addition, since the on-resistance of the tube is very small no matter which way it goes, the RC constant is very small and the conversion speed is very fast. Therefore, the push-pull output stage not only improves the load capacity of the circuit, but also increases the switching speed. For your reference. The
push-pull circuit is two transistors or MOSFETs with the same parameters, which exist in the circuit in a push-pull manner, each responsible for the waveform amplification task of the positive and negative half cycles. When the circuit is working, only one of the two symmetrical power switch tubes is turned on at a time, so the conduction loss is small and the efficiency is high.

Outputs can both sink and draw current from the load