Video acquisition system based on image sensor MT9M111

　　CMOS image acquisition systems generally have image quality problems. If the image is not processed specifically, the image quality is difficult to guarantee. In recent years, with the rapid development of SoC technology, SoC image sensors have emerged in the field of image acquisition and processing. They integrate CMOS sensors and graphics processor functions to obtain very satisfactory image quality. The video acquisition system designed in this paper uses the SoC imaging chip MT9M111 and the USB2.0 interface chip CY7C68013.

　　system structure

　　The principle block diagram of this system is shown in Figure 1. When the image sensor starts working, the collected data is first stored in SRAM1 through the FPGA control logic. After the acquisition/storage process of a frame of image is completed, SRAM1 enters the write end state. At this time, the SRAM is switched, and SRAM2 continues to store the collected data. At the same time, SRAM1 is in a readable state. The control logic in the FPGA controls the data in SRAM1 to be transferred to the USB chip and then to the host. This system adopts a dual SRAM structure and a ping-pong mechanism. The two memories work alternately, so that the image acquisition and transmission are carried out in parallel. The dual frame storage structure not only improves the speed of the system, but also, since most of the algorithms for implementing various image processing in the FPGA require a relatively large storage space, the two large-capacity SRAMs can act as external caches when implementing the algorithms.

　　MT9M111

　　This system uses the MT9M111 SoC product launched by Micron that integrates CMOS sensor and graphics processor. MT9M111 is a low-power, low-cost progressive scan CMOS image sensor; 1.3 million pixel resolution (1280H×1024V); 1/3 inch optical format; power consumption is 170mW at full resolution 15fps, and power consumption is 90mW at VGA resolution 30fps. MT9M111 uses low-leakage DRAM process and is equipped with Micron's patented DigitalClarity technology to provide clear and bright color images even in the worst lighting conditions. MT9M111 has lower dark current and reduces chroma/luminance interference and transient noise. The functions provided by the embedded programmable image stream processor of MT9M111

　　Including color restoration and repair, automatic exposure, white balance, lens shading correction, increased clarity, programmable grayscale correction, dark level offset correction, flicker avoidance, continuous adjustment of filter size, smooth digital zoom, fast automatic exposure mode and non-operating defect correction, etc. Moreover, it is equipped with a two-wire serial interface, through which the USB chip can be configured.

　　IS61WV20488

　　The SRAM parameters related to image processing are mainly the read and write speed and capacity of SRAM. In terms of capacity, the maximum resolution of the image collected by this system is 1280×1024, the data width is 8 bits, and the 2M×8bit SRAM can meet the requirements of storing one frame of image data. The read and write speed of SRAM is generally 12ns, 15ns, 20ns or slower. Since the read and write speed of SRAM directly affects the clock of the entire image processing system, the faster the read and write speed of SRAM, the better. This system uses ISSI's IS61WV20488, with a chip capacity of 2M×8bit.

　　CY7C68013

　　The image data transmission part uses the interface chip CY7C68013 specially used for USB2.0 launched by Cypress. The chip includes an enhanced 8051 processor with 815kB on-chip RAM (compatible with the standard 8051 series, with a speed increase of 3 to 5 times), 4kB FIFO memory and a universal programmable interface I2C bus, a serial interface engine (SIE) and a USB2.0 transceiver.

　　Figure 1 Video acquisition system based on SoC image sensor