STM32 reset/clock control-EEWORLD

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========================== Reset/Clock Control ==================== ===

1. Clock Security System (CSS)

After the clock safety system is activated, the clock monitor will monitor the external high-speed oscillator in real time; if the HSE clock fails, the external oscillator is automatically turned off and a clock safety interrupt is generated, which is connected to the NMI interrupt of the Cortex-M3; at the same time, the CSS switches the internal RC oscillator to the system clock source of the STM32 (for the STM32F103, the clock failure event will also be sent to the brake input of the advanced timer TIM1 to implement motor protection control).

Operating procedures:

1) Start the clock security system CSS: RCC_ClockSecuritySystemCmd(ENABLE); (NMI interrupt is not maskable!)

2) When the external oscillator fails, an NMI interrupt is generated, and the corresponding interrupt program is:

void NMIException(void)

{

if (RCC_GetITStatus(RCC_IT_CSS) != RESET)

{ // HSE and PLL are disabled (but PLL settings remain unchanged)

…… // Customer adds corresponding system protection code

// The following is the preset code after HSE recovery

RCC_HSEConfig(RCC_HSE_ON); // Enable HSE

RCC_ITConfig(RCC_IT_HSERDY, ENABLE); // Enable HSE ready interrupt

RCC_ITConfig(RCC_IT_PLLRDY, ENABLE); // Enable PLL ready interrupt

RCC_ClearITPendingBit(RCC_IT_CSS); // Clear the pending bit of the clock security system interrupt

// At this point, once the HSE clock is restored, an HSERDY interrupt will occur. In the RCC interrupt handler, the system clock can be set to its previous state

}

3) In the RCC interrupt handler, HSE and PLL are processed accordingly.

Note: Once CSS is activated, a CSS interrupt will be generated when the HSE clock fails, and NMI will be automatically generated. NMI will be executed continuously until the CSS interrupt pending bit is cleared. Therefore, the CSS interrupt must be cleared in the NMI handler by setting the CSSC bit in the clock interrupt register (RCC_CIR).

2. SysTick Working Principle

The Cortex-M3 core contains a SysTick clock. SysTick is a 24-bit down counter. After SysTick is set to an initial value and enabled, the count value decreases by 1 after each system clock cycle. When the count reaches 0, the SysTick counter automatically reloads the initial value and continues counting. At the same time, the internal COUNTFLAG flag is set to trigger an interrupt (if the interrupt is enabled).

3. Internal clock output PA.8 (MCO)

The PA.8 pin of STM32 has a multiplexing function - clock output (MCO), which can output the internal clock of STM32 through PA.8.

Operating procedures:

1) Set PA.8 to multiplexed Push-Pull mode.

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_Init(GPIOA, &GPIO_InitStructure);

2) Select the output clock source.

The clock selection is controlled by the MCO[2:0] bits in the clock configuration register (RCC_CFGR).

RCC_MCOConfig(RCC_MCO);

The parameter RCC_MCO is the internal clock to be output:

RCC_MCO_NoClock --- No clock output

RCC_MCO_SYSCLK --- Output system clock (SysCLK)

RCC_MCO_HSI --- Output internal high speed 8MHz RC oscillator clock (HSI)

RCC_MCO_HSE --- Output high-speed external clock signal (HSE)

RCC_MCO_PLLCLK_Div2 --- Output PLL divided-by-two clock after frequency multiplication (PLLCLK/2)

Note: Since the maximum response frequency of the STM32 GPIO output pin is 50MHz, if the output frequency exceeds 50MHz, the output waveform will be distorted.

4. Programmable Voltage Monitor (PVD)

STM32 has a built-in PVD function for monitoring the MCU power supply voltage VDD. The PLS[2:0] bit in the power control register can be used to set the threshold of the monitoring voltage and monitor the power supply by comparing the external voltage. When the condition is triggered, the system needs to enter a special protection state and perform an emergency shutdown task: save some system data and perform corresponding protection operations on peripherals.

Operating procedures:

1) Start PVD after the system starts and enable the corresponding interrupts.

PWR_PVDLevelConfig(PWR_PVDLevel_2V8); //Set monitoring threshold

PWR_PVDCmd(ENABLE); // Enable PVD

EXTI_StructInit(&EXTI_InitStructure);

EXTI_InitStructure.EXTI_Line = EXTI_Line16; // PVD is connected to interrupt line 16

EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; //Use interrupt mode

EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Raising; //Interrupt occurs when the voltage is lower than the threshold

EXTI_InitStructure.EXTI_LineCmd = ENABLE; // Enable interrupt line

EXTI_Init(&EXTI_InitStructure); // Initial

EXTI_InitStructure.EXTI_Trigger assignment options:

EXTI_Trigger_Rising---Indicates that an interrupt is generated when the voltage drops from high to below the set threshold;

EXTI_Trigger_Falling---Indicates that an interrupt is generated when the voltage rises from low to above the set threshold;

EXTI_Trigger_Rising_Falling---Indicates that an interrupt is generated when the voltage rises or falls beyond the set threshold.

2) When the working voltage is lower than the set threshold, a PVD interrupt will be generated and the corresponding processing will be performed in the interrupt program:

void PVD_IRQHandler(void)

{

EXTI_ClearITPendingBit(EXTI_Line16);

…… // User adds emergency processing code

}

Keywords：STM32 Reference address：STM32 reset/clock control

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