AVR microcontroller external interrupt 0, 1, 2 initialization configuration and description

#include
/*1. Status register SREG

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

   I T H S V N Z C

I: Global interrupt enable bit.

    After I is set, individual interrupt enables are controlled by different interrupt registers. If I is 0, interrupts are disabled.

MCU Control Register - MCUCR The MCU control register contains interrupt trigger control bits and general MCU functions.
Bit 7 6 5 4 3 2 1 0 
            SM2 SE SM1 SM0 ISC11 ISC10 ISC01 ISC00
External interrupt 1 is triggered by pin INT1 if the I flag bit and the corresponding interrupt mask bit of the SREG register are set. The MCU first samples the level on the INT1 pin before detecting the edge. If the edge trigger mode or level change trigger mode is selected, a pulse with a duration greater than one clock cycle will trigger an interrupt, and a pulse that is too short cannot guarantee an interrupt. If the low level trigger mode is selected, the low level must be maintained until the current instruction is executed.
SE: MCU sleep enable bit 
SM1~SM0: MCU sleep mode selection

     SM2 SM1 SM0 Sleep mode

      0 0 0 Idle

      0 0 1 ADC noise suppression mode

      0 1 0 Power-down mode

      0 1 1 Power saving mode

      1 0 0 Reserved

      1 0 1 Reserved

      1 1 0 Standby(1) mode

      1 1 1 Extended Standby(1) mode

                           ISC11 ISC10 Description

                             0 0 Generates an interrupt request when INT1 is low

                             0 1 Any logic level change on the INT1 pin will trigger an interrupt

                             1 0 The falling edge of INT1 generates an asynchronous interrupt request

                             1 1 The rising edge of INT1 generates an asynchronous interrupt request
External interrupt 0 is triggered by pin INT0 if the I flag bit of the SREG register and the corresponding interrupt mask bit are set. The MCU first samples the level on the INT0 pin before detecting the edge. If the edge trigger mode or the level change trigger mode is selected, a pulse with a duration greater than one clock cycle will trigger an interrupt, and a pulse that is too short cannot guarantee an interrupt. If the low level trigger mode is selected, the low level must be maintained until the current instruction is executed.

                           ISC01 ISC00 Description

                             0 0 When INT0 is low, an interrupt request is generated.

                             0 1 Any logic level change on the INT0 pin will trigger an interrupt

                             1 0 The falling edge of INT0 generates an asynchronous interrupt request

                             1 1 The rising edge of INT0 generates an asynchronous interrupt request
*/

/*MCU Control and Status Register - MCUCSR -
   Bit 7 6 5 4 3 2 1 0 
              JTD ISC2 - JTRF WDRF BORF EXTRF PORF

                            * Bit 6 – ISC2: Interrupt 2 trigger mode control

                            Asynchronous external interrupt 2 is activated by external pin INT2 if the I flag of the SREG register and the corresponding 
                            interrupt mask bit of the GICR register are set. If ISC2 is written as 0, the falling edge of INT2 activates the interrupt. If ISC2 is written as 1, 
                            the rising activates the interrupt. The edge triggering mode of INT2 is asynchronous. As long as a pulse with a width greater than 50ns
        (1s=1000ms, 1 ms=1000μs, 1μs=1000ns)
                            of the data indicated is generated on the INT2 pin, an interrupt will be triggered. If a low-level interrupt is selected, the low level must be maintained until the current instruction is completed 
                            before an interrupt will be generated. And as long as the pin is pulled low, an interrupt request will be triggered. An interrupt may occur when changing ISC2 
                            . Therefore, it is recommended to clear the corresponding interrupt enable bit INT2 in the GICR register first, and then change ISC2. 
                            Finally, do not forget to clear the corresponding interrupt flag bit INTF2 in the GIFR register by writing '1' to it before re-enabling the interrupt 
                            .

*/

/*
General interrupt control register - GICR

                             Bit 7 6 5 4 3 2 1 0

                                        INT1 INT0 INT2 – – – IVSEL IVCE

                            * Bit 7 – INT1: Enable external interrupt request 1

                            When INT1 is '1' and the I flag of the status register SREG is set, the corresponding external pin interrupt is enabled. The 
                            interrupt sensitivity level control 1 bit 1/0 (ISC11 and ISC10) of the MCU general control register – MCUCR determines whether the interrupt is 
                            triggered by the rising edge, falling edge, or INT1 level. Once enabled, even if the INT1 pin is configured as an output, 
                            as long as the pin level changes accordingly, an interrupt will be generated.

                            * Bit 6 – INT0: Enable external interrupt request 0

                            When INT0 is '1' and the I flag of the status register SREG is set, the corresponding external pin interrupt is enabled. The 
                            interrupt sensitivity level control 0 bit 1/0 (ISC01 and ISC00) of the MCU general control register – MCUCR determines whether the interrupt is 
                            triggered by the rising edge, falling edge, or INT0 level. Once enabled, even if the INT0 pin is configured as an output, 
                            an interrupt will be generated as long as the pin level changes accordingly.

                           * Bit 5 – INT2: Enable external interrupt request 2

                            When INT2 is '1' and the I flag of the status register SREG is set, the corresponding external pin interrupt is enabled. The 
                           interrupt sensitivity level control 2 bits 1/0 (ISC2 and ISC2) of the MCU general control register – MCUCR determine whether the interrupt is 
                           triggered by the rising edge, falling edge, or INT2 level. Once enabled, even if the INT2 pin is configured as an output, 
                           as long as the pin level changes accordingly, the interrupt can be generated.

*/
/*
General interrupt flag register - GIFR

                            Bit 7 6 5 4 3 2 1 0

                                       INTF1 INTF0 INTF2 – – – – –

                           * Bit 7 – INTF1: External interrupt flag 1

                           When the level of the INT1 pin changes, an interrupt request is triggered and the corresponding interrupt flag INTF1 is set. If bit 
                           I of SREG and the corresponding interrupt enable bit INT1 of the GICR register are "1", the MCU jumps to the corresponding interrupt vector. The flag is automatically cleared after entering the 
                           interrupt service routine. In addition, the flag bit can also be cleared by writing "0".

                           * Bit 6 – INTF0: External interrupt flag 0

                           When the level of the INT0 pin changes, an interrupt request is triggered and the corresponding interrupt flag INTF0 is set. If bit 
                           I of SREG and the corresponding interrupt enable bit INT0 of the GICR register are "1", the MCU jumps to the corresponding interrupt vector. The flag is automatically cleared after entering the 
                           interrupt service routine. In addition, the flag bit can also be cleared by writing "0".

                           * Bit 5 – INTF2: External interrupt flag 2

                           When the INT2 pin level changes, an interrupt request is triggered and the corresponding interrupt flag INTF2 is set. If bit 
                           I of SREG and the corresponding interrupt enable bit INT2 of the GICR register are "1", the MCU jumps to the corresponding interrupt vector. The flag is automatically cleared after entering the 
                           interrupt  service routine. In addition, the flag bit can also be cleared by writing "0". Note that
                           when the INT2 interrupt is disabled and enters certain sleep modes, the input buffer of the pin will be disabled. This will cause 
                           the logic change of the INTF2 flag setting signal

*/
//External interrupt 0 vector port
#pragma interrupt_handler INTER_0:iv_INT0 
//External interrupt 1 vector port
#pragma interrupt_handler INTER_1:iv_INT1 
//External interrupt 2 vector port         
#pragma interrupt_handler INTER_2:iv_INT2

void INTER_init_0(unsigned char a)//a takes the value 0-3
{
switch(a)
{
case 0:MCUCR&=~(1< case 1:MCUCR&=~(1< case 2:MCUCR|=1< case 3:MCUCR|=1< default : MCUCR|=1< }
GICR|=(1< GIFR&=~(1< SREG|=0x80;//Enable global interrupt
}
void INTER_init_1(unsigned char a)//a takes the value 0-3
{
switch(a)
{
case 0:MCUCR&=~(1< case 1:MCUCR&=~(1< case 2:MCUCR|=1< case 3:MCUCR|=(1< default : MCUCR|=1< }
GICR|=(1< GIFR&=~(1< SREG|=0x80;//Enable global interrupt

}
void INTER_init_2(unsigned char a)
{
if(a)
MCUCSR|=(1< else 
MCUCSR&=~(1<

GICR|=(1< GIFR&=~(1< SREG|=0x80;//Enable global interrupt
}
void INTER_0(void)
{

//add your code here!

} 
void INTER_1(void)
{

//add your code here!

}
void INTER_2(void)
{

//add your code here!

}