MSP430 Learning Clock

Clock initialization and GPIO

Overview:

The purpose of this lab is to understand the steps used to perform the initialization process for an MSP430 Value Line device. In this exercise, you will write the initialization code and run the device using various clock resources.

1. Write initialization code

2. The source of MCLK for running CPU: VLO, 32768 crystal, DCO

3. Main program part

4. Observe the LED flash speed

 

MSP430 Clock:

1. There are three or four clock sources in the MSP430 microcontroller:

(1) LFXT1CLK is a low-speed/high-speed crystal oscillator source, usually connected to 32.768kHz, but can also be connected to (400kHz~16Mhz);

(2) XT2CLK, optional high-frequency oscillator, external standard high-speed crystal oscillator, usually 8Mhz, can also be connected to (400kHz ~ 16Mhz);     

(3) DCOCLK, digitally controlled oscillator, is an internal crystal oscillator consisting of an RC oscillation circuit;

(4) VLOCLK, internal low frequency oscillator, 12kHz standard oscillator.

2. There are three clock systems inside the MSP430 microcontroller:

(1) ACLK, Auxiliary Clock, usually uses LFXT1CLK or VLOCLK as the clock source, and the clock division factor can be changed through software control;    

(2) MCLK, Master Clock, system master clock unit, provides clock for the system core, which can be selected from four clock sources by software;

(3) SMCLK, Sub-Main Clock, system sub-clock, the clock source can also be selected by software.

Basic Clock Module Registers

DCO control register                         DCOCTL

Basic clock system control 1                   BCSCTL1

Basic clock system control 2                   BCSCTL2

Basic clock system control 3                   BCSCTL3

SFR interrupt enable register 1                 IE1

SFR interrupt flag register 1                   IFG1

3. The clock setting of MSP430 includes 3 registers, DCOCTL, BCSCTL1, BCSCTL2, BCSCTL3

 

DCOCTL, DCO control register, address is 56H, initial value is 60H

 

DCO2

DCO1

DCO0

MOD4

MOD3

MOD2

MOD1

MOD0

 

DCO0~DCO2: DCO Select Bit, defines one of 8 frequencies, and the frequency is defined by the current injected into the DC generator.

MOD0~MOD4: Modulation Bit, frequency fine-tuning.

Generally, when DCO is not needed, just keep the default initial value.

BCSCTL1, Basic Clock System Control 1, address is 57H, initial value is 84H

 

XT2OFF

XTS

DIVA1

DIVA0

XT5V

RSEL2

RSEL1

RSEL0

 

RSEL0~RSEL2: Select an internal resistor to determine the nominal frequency. 0 is the lowest and 7 is the highest.

XT5V: 1.

DIVA0~DIVA1: Select the frequency division coefficient of ACLK. DIVA=0,1,2,3, the frequency division coefficients of ACLK are 1,2,4,8 respectively;

XTS: Select whether LFXT1 operates in low-frequency crystal mode (XTS=0) or high-frequency crystal mode (XTS=1).

XT2OFF: Controls the XT2 oscillator on (XT2OFF=0) and off (XT2OFF=1).

Under normal circumstances, resetting XT2OFF is sufficient.

BCSCTL2, Basic Clock System Control 2, address is 58H, initial value is 00H

 

SEM1

SELM0

DIVM1

DIVM0

BY MYSELF

DIVS1

DIVS0

DCOR

 

DCOR: Enable External Resistor. 0, select internal resistor; 1, select external resistor

DIVS0~DIVS1: DIVS=0,1,2,3 corresponds to SMCLK division factors of 1,2,4,8

SELS: Select the clock source of SMCLK, 0: DCOCLK; 1: XT2CLK/LFXTCLK.

DIVM0~1: Select the division factor of MCLK, DIVM=0,1,2,3 corresponds to the division factors of 1,2,4,8.

SELM0~1: Select the clock source of MCLK, 0,1:DCOCLK, 2:XT2CLK, 3:LFXT1CLK

When I use it, I usually select XT2 as the clock source for SMCLK and MCLK.

other:

1. LFXT1: A valid PUC signal will reset OSCOFF and allow LFXT1 to work. If the LFXT1 signal is not used as SMCLK or MCLK, the software can set OSCOFF to shut down LFXT1.

2. XT2: XT2 generates the XT2CLK clock signal. If the XT2CLK signal is not used as the clock MCLK and SMCLK, XT2 can be turned off by setting XT2OFF. The PUC signal is then set to XT2OFF, which means that XT2 is turned off.

3. DCO oscillator: When the oscillator fails, the DCO oscillator will be automatically selected as the clock source of MCLK. If the DCO signal is not used as the SMCLK and MCLK clock signals, the SCG0 bit can be set to turn off the DCO DC generator.

4. After the PUC signal, DCOCLK is used as the clock signal of MCLK. The clock source of MCLK can be set to LFXT1 or XT2 as needed. The setting sequence is as follows:

(1)清OSCOFF/XT2

(2) Clear OFIFG

(3) Delay waiting for at least 50uS

(4) Check OFIFG again. If it is still set, repeat steps (1)-(4) until OFIFG = 0.

(5) Set the corresponding SELM of BCSCTL2.

 

Case Analysis

1. The CPU runs under the VLO clock:

This is the slowest clock, running at about 12 kHz. Therefore, we will visualize this by having the LED flash red slowly at a rate of about every 3 seconds. We can leave the clock system in this state by default, set up to operate exclusively on the VLO. We will not be using any of the ALCK peripheral clocks in this lab, but you should realize that ACLK is derived from the VLO clock.

#include

void main(void)

{

WDTCTL = WDTPW + WDTHOLD; // Turn off the watchdog timer

P1DIR = 0x40; // P1.6 configure output

P1OUT = 0; // Turn off LED

BCSCTL3 |= LFXT1S_2;                   // LFXT1 = VLO

IFG1 &= ~OFIFG; // Clear OSCFault flag

__bis_SR_register(SCG1 + SCG0); // Turn off DCO

BCSCTL2 |= SELM_3 + DIVM_3; // MCLK = VLO/8

while(1)

{

P1OUT = 0x40; // Turn on LED

_delay_cycles(100);

P1OUT = 0; // Turn off LED

_delay_cycles(5000);

}

}

2. The CPU runs at the crystal oscillator (32768Hz) clock:

The crystal frequency is 32768 Hz, about 3 times VLO. If we used the crystal in the previous code, the LED should flash about once per second. Do you know why 32768 Hz is a standard? It's because this number is 2 to the 15th power, so it's easy to use a simple digital counting circuit to get a rate of once per second - for watches and other time bases. Realize that ACLK comes from the external crystal clock.

#include

void main(void)

{

WDTCTL = WDTPW + WDTHOLD; // Turn off the watchdog timer

P1DIR = 0x41; // P1.0 and P1.6 configure output

P1OUT = 0x01; // Turn on P1.0

BCSCTL3 |= LFXT1S_0; // LFXT1 = 32768Hz crystal

while(IFG1 & OFIFG)

{

IFG1 &= ~OFIFG; // Clear OSCFault flag

_delay_cycles(100000); // Delay for visible logo

}

P1OUT = 0; // Turn off P1

__bis_SR_register(SCG1 + SCG0); // Turn off DCO

BCSCTL2 |= SELM_3 + DIVM_3; // MCLK = 32768/8

while(1)

{

P1OUT = 0x40; // Turn on LED

_delay_cycles(100);

P1OUT = 0; // Turn off LED

_delay_cycles(5000);

}

}

3. The CPU runs on the crystal oscillator (32768Hz) and DCO clock:

The slowest frequency we can run the DCO at is about 1MHz (which is also the default speed). Therefore, we will start by switching the MCLK to the DCO. In most systems, you will want ACLK to run on a VLO or 32768 Hz crystal. Since ACLK in our current code is running on a crystal, we will turn on the DCO calculations.

#include

void main(void)

{

WDTCTL = WDTPW + WDTHOLD; // Turn off the watchdog timer

if (CALBC1_1MHZ ==0xFF || CALDCO_1MHZ == 0xFF)

{

while(1);                               // If cal const erased, 挂起

}

BCSCTL1 = CALBC1_1MHZ;                // Set range

DCOCTL = CALDCO_1MHZ; //Set DCO mode

P1DIR = 0x41; // P1.0 and P1.6 configure output

P1OUT = 0x01; // P1.0 is turned on

BCSCTL3 |= LFXT1S_0;                   // LFXT1 = 32768Hz

while(IFG1 & OFIFG)

{

IFG1 &= ~OFIFG; // Clear OSCFault flag

_delay_cycles(100000); // Delay for visible flag

}

P1OUT = 0; // P1.6 is off

// __bis_SR_register(SCG1 + SCG0); // Turn off DCO

BCSCTL2 |= SELM_0 + DIVM_3; // MCLK = DCO

while(1)

{

P1OUT = 0x40; // P1.6 is turned on

_delay_cycles(100);

P1OUT = 0; // P1.6 is turned off

_delay_cycles(5000);

}

}

4. CPU runs under DCO clock:

The slowest frequency we can run the DCO at is about 1MHz (which is also the default speed). Therefore, we will start by switching the MCLK to the DCO. In most systems, you will want to run ACLK at VLO or a crystal. Since ACLK is running at VLO in our current code, we will turn on the DCO to run.

#include

void main(void)

{

WDTCTL = WDTPW + WDTHOLD; // Turn off the watchdog timer

if (CALBC1_1MHZ ==0xFF || CALDCO_1MHZ == 0xFF)

{

while(1);                                   // If cal const erased,挂起

}

BCSCTL1 = CALBC1_1MHZ;                     // Set range

DCOCTL = CALDCO_1MHZ; //Set DCO mode

P1DIR = 0x40; // P1.6 configure output

P1OUT = 0; // P1 is turned off

BCSCTL3 |= LFXT1S_2;                        // LFXT1 = VLO

IFG1 &= ~OFIFG; // Clear OSCFault flag

//__bis_SR_register(SCG1 + SCG0); // Turn off DCO

BCSCTL2 |= SELM_0 + DIVM_3; // MCLK = DCO/8

while(1)

{

P1OUT = 0x40; // P1.6 is turned off

_delay_cycles(100);

P1OUT = 0; // P1.6 is turned on

_delay_cycles(5000);

}

}

The following will analyze the subtle differences in the code of the above 4 examples:

First, let's take a look at the contents of the msp430x20x2.h file. Since the header file contains a lot of information, we will only briefly explain the parts related to the above four codes. Please read the rest by yourself.

 

1. WDTCTL = WDTPW + WDTHOLD; // Turn off the watchdog timer (Examples 1, 2, 3, 4)

The relevant descriptions in the header file are as follows:

/************************************************************

* WATCHDOG TIMER

************************************************************/

#define __MSP430_HAS_WDT__      /* Definition to show that Module is available */

SFR_16BIT(WDTCTL);                /* Watchdog Timer Control */

/* The bit names have been prefixed with "WDT" */

#define WDTIS0                 (0x0001)

#define WDTIS1                 (0x0002)

#define WDTSSEL                (0x0004)

#define WDTCNTCL              (0x0008)

#define WDTTMSEL               (0x0010)

#define WDTNMI                 (0x0020)

#define WDTNMIES               (0x0040)

#define WDTHOLD                (0x0080)

#define WDTPW                  (0x5A00)

This command sets the password (WDTPW) and the stop bit timer (WDTHOLD). All WatchDog configurations need to be completed with the assistance of WDTPW.

Here are some examples:

A. The interval time is encoded by Bit0-2:

1. The watchdog clock is FSMCLK (assuming it is 1MHz)

#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL)                         /* 32ms interval (default) */

#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0)                  /* 8ms     " */

#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1)                  /* 0.5ms   " */

#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0)           /* 0.064ms " */

 

2. The watchdog clock is FACLK (assumed to be 32KHz)

#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL)                 /* 1000ms  " */

#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0)          /* 250ms   " */

#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1)          /* 16ms    " */

 

B. Watchdog mode - restart after expiration time:

1. The watchdog clock is FSMCLK (assuming it is 1MHz)

#define WDT_MRST_32         (WDTPW+WDTCNTCL)                                  /* 32ms interval (default) */

#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS0)                           /* 8ms     " */

#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS1)                           /* 0.5ms   " */

#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS1+WDTIS0)                    /* 0.064ms " */

 

2. The watchdog clock is FACLK (assumed to be 32KHz)

#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */

#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */

#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */

#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */

 

2. P1DIR = 0x40; // P1.6 configuration output

    P1OUT = 0; // P1 is turned off (Example 1, 2, 3, 4)

DIR and P1OUT configure the direction and output value of the IO port respectively. I will not go into details here. Please refer to the manual.

 

3. BCSCTL3 |= LFXT1S_2; // LFXT1 = VLO (Example 1 and Example 4)

    BCSCTL3 |= LFXT1S_0; // LFXT1 = 32768Hz (Example 2 and Example 3)

/************************************************************

* Basic Clock Module

************************************************************/

#define __MSP430_HAS_BC2__                   

/* Definition to show that Module is available */

 

SFR_8BIT(DCOCTL);                         /* DCO Clock Frequency Control */

SFR_8BIT(BCSCTL1);                        /* Basic Clock System Control 1 */

SFR_8BIT(BCSCTL2);                        /* Basic Clock System Control 2 */

SFR_8BIT(BCSCTL3);                        /* Basic Clock System Control 3 */

 

#define MOD0                   (0x01)         /* Modulation Bit 0 */

#define MOD1                   (0x02)         /* Modulation Bit 1 */

#define MOD2                   (0x04)         /* Modulation Bit 2 */

#define MOD3                   (0x08)         /* Modulation Bit 3 */

#define MOD4                   (0x10)         /* Modulation Bit 4 */

#define DCO0                   (0x20)         /* DCO Select Bit 0 */

#define DCO1                   (0x40)         /* DCO Select Bit 1 */

#define DCO2                   (0x80)         /* DCO Select Bit 2 */

                                                                                 

#define LFXT1OF                (0x01)        

/* Low/high Frequency Oscillator Fault Flag */

#define XT2OF                  (0x02)        

/* High frequency oscillator 2 fault flag */

#define XCAP0                  (0x04)       /* XIN/XOUT Cap 0 */

#define XCAP1                  (0x08)       /* XIN/XOUT Cap 1 */

#define LFXT1S0                (0x10)       /* Mode 0 for LFXT1 (XTS = 0) */

#define LFXT1S1                (0x20)       /* Mode 1 for LFXT1 (XTS = 0) */

#define XT2S0                  (0x40)       /* Mode 0 for XT2 */

#define XT2S1                  (0x80)       /* Mode 1 for XT2 */

 

#define XCAP_0                 (0x00)         /* XIN/XOUT Cap : 0 pF */

#define XCAP_1                 (0x04)         /* XIN/XOUT Cap : 6 pF */

#define XCAP_2                 (0x08)         /* XIN/XOUT Cap : 10 pF */

#define XCAP_3                 (0x0C)         /* XIN/XOUT Cap : 12.5 pF */

 

#define LFXT1S_0               (0x00)        

/* Mode 0 for LFXT1 : Normal operation */

#define LFXT1S_1               (0x10)     /* Mode 1 for LFXT1 : Reserved */

#define LFXT1S_2               (0x20)     /* Mode 2 for LFXT1 : VLO */

#define LFXT1S_3               (0x30)    

/* Mode 3 for LFXT1 : Digital input signal */

 

#define XT2S_0                 (0x00)    /* Mode 0 for XT2 : 0.4 - 1 MHz */

#define XT2S_1                 (0x40)    /* Mode 1 for XT2 : 1 - 4 MHz */

#define XT2S_2                 (0x80)    /* Mode 2 for XT2 : 2 - 16 MHz */

#define XT2S_3                 (0xC0)       

 /* Mode 3 for XT2 : Digital input signal */

 

4. __bis_SR_register(SCG1 + SCG0); // Turn off DCO

 

__bis_SR_register() is defined in the intrinsics.h header file, and its function is to set the position in SR to zero.

About the role of code in header files

#ifdef __cplusplus

extern "C"

{

#endif

#ifdef __cplusplus

}

#endif /* extern "C" */

It is generally used to output C++ code in standard C form (that is, it is called in C form). This is because although C++ is often considered a superset of C, the compiler of C++ is different from the compiler of C. It is safe to define it in this way when calling C++ code from C.

 

BCSCTL2 |= SELM_3 + DIVM_3; // MCLK = VLO/8

    BCSCTL2 |= SELM_3 + DIVM_3; // MCLK = 32768/8

    BCSCTL2 |= SELM_0 + DIVM_3; // MCLK = DCO

    BCSCTL2 |= SELM_0 + DIVM_3; // MCLK = DCO/8

The following definitions are available in MSP430:

#define RSEL0                  (0x01)         /* Range Select Bit 0 */

#define RSEL1                  (0x02)         /* Range Select Bit 1 */

#define RSEL2                  (0x04)         /* Range Select Bit 2 */

#define RSEL3                  (0x08)         /* Range Select Bit 3 */

#define DIVA0                  (0x10)         /* ACLK Divider 0 */

#define DIVA1                  (0x20)         /* ACLK Divider 1 */

#define XTS                    (0x40)       

 /* LFXTCLK 0:Low Freq. / 1: High Freq. */

#define XT2OFF                 (0x80)         /* Enable XT2CLK */

 

#define DIVA_0                 (0x00)         /* ACLK Divider 0: /1 */

#define DIVA_1                 (0x10)         /* ACLK Divider 1: /2 */

#define DIVA_2                 (0x20)         /* ACLK Divider 2: /4 */

#define DIVA_3                 (0x30)         /* ACLK Divider 3: /8 */

 

#define DIVS0                  (0x02)         /* SMCLK Divider 0 */

#define DIVS1                  (0x04)         /* SMCLK Divider 1 */

#define SELS                   (0x08)       

 /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */

#define DIVM0                  (0x10)         /* MCLK Divider 0 */

#define DIVM1                  (0x20)         /* MCLK Divider 1 */

#define SELM0                  (0x40)         /* MCLK Source Select 0 */

#define SELM1                  (0x80)         /* MCLK Source Select 1 */

 

#define DIVS_0                 (0x00)         /* SMCLK Divider 0: /1 */

#define DIVS_1                 (0x02)         /* SMCLK Divider 1: /2 */

#define DIVS_2                 (0x04)         /* SMCLK Divider 2: /4 */

#define DIVS_3                 (0x06)         /* SMCLK Divider 3: /8 */

 

#define DIVM_0                 (0x00)         /* MCLK Divider 0: /1 */

#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */

#define DIVM_2                 (0x20)         /* MCLK Divider 2: /4 */

#define DIVM_3                 (0x30)         /* MCLK Divider 3: /8 */

 

#define SELM_0                 (0x00)    /* MCLK Source Select 0: DCOCLK */

#define SELM_1                 (0x40)    /* MCLK Source Select 1: DCOCLK */

#define SELM_2                 (0x80)   

/* MCLK Source Select 2: XT2CLK/LFXTCLK */

#define SELM_3 (0xC0)        

/* MCLK Source Select 3: LFXTCLK */

 

6. BCSCTL1 = CALBC1_1MHZ; //Set value (Example 3, 4)

#ifndef __DisableCalData

SFR_8BIT(CALDCO_16MHZ);          /* DCOCTL  Calibration Data for 16MHz */

SFR_8BIT(CALBC1_16MHZ);          /* BCSCTL1 Calibration Data for 16MHz */

SFR_8BIT(CALDCO_12MHZ);          /* DCOCTL  Calibration Data for 12MHz */

SFR_8BIT(CALBC1_12MHZ);          /* BCSCTL1 Calibration Data for 12MHz */

SFR_8BIT(CALDCO_8MHZ);           /* DCOCTL  Calibration Data for 8MHz */

SFR_8BIT(CALBC1_8MHZ);           /* BCSCTL1 Calibration Data for 8MHz */

SFR_8BIT(CALDCO_1MHZ);           /* DCOCTL  Calibration Data for 1MHz */

SFR_8BIT(CALBC1_1MHZ);           /* BCSCTL1 Calibration Data for 1MHz */

#endif                              /* #ifndef __DisableCalData */

 

Relevant instructions about SFR_8BIT:

External references resolved by a device-specific linker command file

(Device-specific connector command files for external reference resolution)

#define SFR_8BIT(address)   extern volatile unsigned char address

#define SFR_16BIT(address)  extern volatile unsigned int address

 

七、if (CALBC1_1MHZ ==0xFF || CALDCO_1MHZ == 0xFF)

    {

     while(1);                            // If cal const erased,挂起

} (Example 3, Example 4)

Please note the pitfall here. It can clear the memory segment information.

 

8. IFG1 &= ~OFIFG; // Clear OSCFault flag (Example 1, Example 4)

The clock system will force the DCO to use MCLK as its source in the presence of a clock fault. Therefore, we must clear the fault flag.

The FG1 interrupt flag register is 1. The bit field in the register is the only oscillator fault interrupt flag - OFIFG.

 

9. while(IFG1 & OFIFG)

{

IFG1 &= ~OFIFG; // Clear OSCFault flag

_delay_cycles(100000); // Delay for visible flag

} (Example 2, Example 3)

In the code above we clear the OSCFault flag to continue doing our work, since the clock system will default to VLO. Now, we want to make sure that this flag remains cleared, meaning the crystal is up and running.

If the fault flag is clear, we exit the loop. We need to wait 50 microseconds after the flag is cleared until we test it again. The _delay_cycles(100000). We need it to be that long so we can see the LED light at the beginning of the code. Otherwise, it will go so fast that our light won't be able to see it.

Configuration:

 

	BCSCTL1	BCSCTL2	BCSCTL3	DCOCTL	IFG1
VLO(12KHz)		SELM_3 + DIVM_3	LFXT1S_2
32768KHz		SELM_3 + DIVM_3	LFXT1S_0		While
Crystal oscillator, DCO		SELM_0+ DIVM_3	LFXT1S_0		While
DCO	CALBC1_1MHZ	SELM_0+ DIVM_3	LFXT1S_2	CALDCO_1MHZ

 

result:

 

	ACLK	MCLK	LFXT1
VLO(12KHz)	VLO	VLO/8	VLO
32768Hz	32768Hz	32768Hz/8	32768Hz
Crystal oscillator, DCO	32768Hz	DCO	32768Hz
DCO	VLO	DCO/8	VLO