I have used two series of 430 single-chip microcomputers, MSP430F149 and MSP430F437. The clock settings are slightly different for different series. Let's talk about the clock of 149 step by step!
In f149, the basic clock is called basic clock module, which
has three clock sources:
one LFXT1CLK, which is a low-speed/high-speed crystal oscillator source, usually connected to 32.768khz, can also be connected to (400khz~8Mhz)
one is XT2CLK, an external standard high-speed crystal oscillator, usually connected to 8Mhz, can also be connected to (400khz~8Mhz)
and another one is called DCOCLK, which is an internal crystal oscillator, composed of an RC oscillation circuit.
There are three clock systems in 430.
One is ACLK, which is usually based on LFXT1CLK as the clock source. The frequency division system tree of the clock can be controlled by software.
One is MCLK, which is the Main CLK. It is the main clock unit that provides the clock for the system core. It can be selected from three clock sources by software.
One is SMCLK, which is called the auxiliary main clock. The clock source can also be selected by software.
Basic Clock Module Registers (Basic Clock Registers)
DCO control register DCOCTL
Basic clock system control 1 BCSCTL1
Basic clock system control 2 BCSCTL2
SFR interrupt enable register 1 IE1
SFR interrupt flag register 1 IFG1
The DCOCTL register is used to configure DCOCLK.
BCSCTL1 and BCSCTL2 registers are more important. These two registers control the working clock system of 430 in your entire system.
BCSCTL1 register:
7 6 5 4 3 210
XT2OFF XTS DIVAx XT5V RSELx
XT20FF: Used to control the opening and closing of the XT2 crystal oscillator, set to 1 to close, set to 0 to open
XTS: Used to select the working mode of the low-speed crystal (can be ignored)
DIVAx: Used to select the division coefficient of ACLK
XT5V: Not used
RSELx: Select the resistor (not used, usually set to 0)
BCSCTL2
7 6 5 4 3 2 1 0
SELMx DIVMx SELS DIVSx DOCR
SELMx: Select the clock source of MCLK,
00 DCOCLK
01 DCOCLK
10 XT2CLK
11 LFX1CLK
DIVMx: MCLK division
00 1 division
01 2 division
10 4 division
11 8-division
SELS: clock source of SMCLK, built-in DCO at 0, external high-speed XT2 at 1
DIVSx: frequency division of SMCLK, same as MCLK frequency division
DCOR: whether the resistor controlling the frequency is internal or external (never used)
Example initialization program
void Init_CLK(void)
{
unsigned int i;
BCSCTL1=0x00; //XT2 is turned on, LFXTCLK is in low-frequency mode, ACLK frequency division is 0
do
{
IFG1&=~OFIFG;
for(i=0x20;i>0;i--);
}
while((IFG1&OFIFG)==OFIFG); //When OSCFault=1, that is, the crystal oscillator does not oscillate, wait
BCSCTL2=0X00;
BCSCTL2|=SELM1; //MCLK clock is XT2,
BCSCTL2|=SELS; //SMCLK clock is XT2
}
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Recommended ReadingLatest update time:2024-11-16 21:30
Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
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