The byte address of port P0 is 80H, and the bit address is 80H to 87H. Each bit line of port P0 has the same but independent logic circuit. The circuit diagram of the bit structure of a certain bit of port P0 is shown in Figure 2.10.
The circuit of a certain bit of P0 port includes:
(1) A data output latch, used to latch the data bits.
(2) Two three-state data input buffers, used for input buffering of latch data and pin data respectively.
(3) A multiplexer switch MUX, one input of which comes from the latch and the other input is "address/data". The input switching is controlled by the "control" signal. The reason for setting up a multiplexer switch is that the PO port can be used as a general I/O port and as the address/data line of the microcontroller system. That is, under the action of the control signal, the MUX realizes the connection and switching between the latch output and the address/data line.
(4) The data output drive and control circuit consists of two field effect transistors (FETs), with the upper field effect transistor forming the pull-up circuit.
In practical applications, the P0 port is used as the address/data line of the single-chip microcomputer system in most cases. When transmitting the address or data, the CPU sends a control signal to open the upper AND gate, so that the multiplexer MUX is turned up, so that the internal address/data line and the lower field effect tube are connected in reverse phase. At this time, the output drive circuit forms a push-pull circuit structure because the upper and lower FETs are in reverse phase, which greatly improves the load capacity. When inputting data, the data signal directly enters the internal bus from the pin through the input buffer.
Port P0 can also be used as a general I/O port. At this time, the control signal sent by the CPU is low , blocking the AND gate and turning off the pull-up field effect transistor of the output drive circuit , while the multi-way transfer switch MUX is turned down and connected to the Q end of the D latch.
When the P0 port is used as an output port, the data output path is composed of a latch and a drive circuit. Since the path already has an output latch, the data output can be directly connected to the peripheral device without adding a data latch circuit. When outputting data, the write pulse from the CPU is added to the CP end of the D latch, the data is written into the D latch, and output to the port pin. However, it should be noted that since the output circuit is an open-drain circuit, an external pull-up resistor must be connected to have a high-level output .
When the P0 port is used as an input port, it is necessary to distinguish between reading pins and reading ports (or reading latches). For this purpose, there are two three-state buffers for reading in the P0 port circuit. The so-called reading pins is to read the data on the pins of the chip. At this time, the buffer below is used, and the buffer is opened by the "read pin" signal. The data on the pin is read in through the buffer through the internal bus; while the reading port is to read the state of the latch Q end through the upper buffer.
The above content is quoted from "New MCS-51 Single Chip Microcomputer Application Design"
Circuit Simulation Diagram
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