2440 Interrupt Management

       Interrupt is the most important concept in embedded systems. Generally, a system uses either interrupt or polling for a device. Interrupt can effectively reduce the processor load, but if a large number of interrupts are used, the processing speed may be reduced because interrupt processing destroys the pipeline mechanism of the processor. Review the interrupt processing process and interrupt mechanism in microcomputer principles.   

       2440 supports FIQ (fast interrupt) and IRQ (normal interrupt) interrupt modes. Generally, only IRQ interrupt is used. 2440 has 60 interrupt sources and does not support interrupt nesting. For details, refer to Chapter 14 of the user manual. The following figure shows the interrupt generation process of 2440.

For more details, please refer to the user manual for registers.

    There are two types of interrupt sources, sub-interrupt interrupt sources and interrupt sources. When a sub-interrupt generates an interrupt signal, the corresponding bit of the sub-interrupt source pending register (SUBRCPND) is automatically set to 1, and the sub-interrupt mask register (SUBMASK) is checked to see if the sub-interrupt is masked (manually set). If not, the interrupt source register (SRCPND) is set to 1 to check whether the interrupt source is masked and which mode is used. If not, the IRQ mode is used. After priority judgment, the high priority is executed, and the interrupt pending register is set to 1 to generate an IRQ signal. At the same time, the I position of the CPSR register is 1, indicating that an IRQ interrupt is currently generated. Remember that I asked everyone to pay attention to the I and Q bits in this register before, and this is its role.

Interrupt handling process:

    Each time the CPU executes an instruction, it checks the CPSR register. When it finds that the I and F bits are set to 1, it performs interrupt processing. The first step is to jump into the exception vector table:

    b       ResetHandler

       b     HandlerUndef  ;handler for Undefined mode

       b     HandlerSWI    ;handler for SWI interrupt

       b     HandlerPabort ;handler for PAbort

       b     HandlerDabort ;handler for DAbort

       b     .             ;reserved

       b     HandlerIRQ    ;handler for IRQ interrupt

       b     HandlerFIQ     ;handler for FIQ interrupt

HandlerFIQ HANDLER HandleFIQ

HandlerIRQ HANDLER HandleIRQ

HandlerUndef HANDLER HandleUndef

HandlerSWI      HANDLER HandleSWI

HandlerDabort TRADE HandlerDabort

HandlerPassport TRADE HandlerPassport

       ^   _ISR_STARTADDRESS        ; _ISR_STARTADDRESS=0x33FF_FF00

HandleReset #4

HandleUndef #4

HandleSWI            #   4

HandlePabort # 4

Handle Abort #4

HandleReserved # 4

HandleIRQ # 4

HandleFIQ             #   4

If it is IRQ, it jumps to HandlerIRQ, which is done by hardware.

    ldr r0,=HandleIRQ       ;This routine is needed

    ldr r1,=IsrIRQ    ;if there is not 'subs pc,lr,#4' at 0x18, 0x1c

    str r1,[r0]

Make a second jump to the level 2 interrupt vector table

IsrIRQ

    sub sp,sp,#4       ;reserved for PC

    stmfd sp!,{r8-r9}

    ldr r9,=INTOFFSET

    ldr r9,[r9]

    ldr r8,=HandleEINT0

    add r8,r8,r9,lsl #2

    ldr r8,[r8]

    str r8,[sp,#8]

    ldmfd   sp!,{r8-r9,pc}

HandleEINT0 # 4

HandleEINT1     #   4

HandleEINT2 # 4

HandleEINT3     #   4

This code completes the establishment of a 2-level interrupt vector table. In our interrupt program, we first register the interrupt

Example: EINT0 = ISR_FUNC(); This completes the association between the interrupt vector and the interrupt service routine. After jumping to the level 2 interrupt vector table, the interrupt processing routine is entered. After the interrupt processing is completed, the CPU returns to continue executing the next program before the interrupt processing. For the protection part of the processing site, refer to the micro-original part.

The following is a test question about interrupt handling functions: Understand the use of interrupt handling functions

Interrupts are an important part of embedded systems, which has led many compiler developers to provide an extension to standard C to support interrupts. The representative fact is that a new keyword

__interrupt. The following code uses the __interrupt keyword to define an interrupt service routine (ISR). Please comment on this code.

__interrupt double compute_area (double radius)

{

 double area = PI * radius * radius;

 printf("\nArea = %f", area);

 return area;

}

The above is the interrupt generation and processing process of 2440. These are the most basic knowledge that must be firmly grasped. For ARM, these are the same, except that the registers may be different, but the processing process is the same. Some processors support reentrant interrupts, such as the 710 processor. Read the priority section in Chapter 14 of the user manual and pay attention to the method of clearing some registers.