ARM interrupt learning and variable length

The PHILIPS ARM controller LPC2000 series is used

1.I/O configuration

LPC2000 has pin function configuration registers. A pin can have 1 to 4 functions (some have only one) through the configuration of PINSEL0~2. However, it does not mean that any pin can be configured as any function. You can only select one of the specified functions according to the provisions of the device manual.

2. Interruption

LPC2000 interrupts are managed by a set of registers called VIC (Vector Interrupt Controller).

The Vectored Interrupt Controller (VIC) has 32 interrupt request inputs that can be programmed into 3 categories: FIQ, Vectored IRQ and Non-Vectored IRQ. The programmable assignment mechanism means that the interrupt priorities of different peripherals can be dynamically assigned and adjusted.

The so-called FIQ is a fast interrupt, which requires the highest priority. If more than one request is assigned to FIQ, VIC will "OR" the interrupt requests and generate a FIQ signal to the ARM processor. When only one interrupt is assigned to FIQ, the shortest FIQ waiting time can be achieved because the FIQ service program can simply start the device processing. However, if more than one interrupt is assigned to the FIQ level, the FIQ service program reads a word from the VIC to identify which FIQ interrupt source generated the interrupt request.

Vector IRQ has medium priority, which means that IRQ can be divided into 16 priorities. The priority of the module is arranged according to VICVectAddr0~15, 0 is the highest level and 15 is the lowest priority.

Non-vectored IRQ has the lowest priority. Multiple interrupts share one interrupt service routine (ISR) entry. The entry address is placed in VICDefVectAddr, and the interrupt status is read to determine which interrupt is responded.

The selection of FIQ and IRQ is configured by registers VICIntEnable and VICIntSelect. Vector IRQ and non-vector IRQ are selected by the 5th bit of VICVectCntl0~15. The interrupt corresponding to the interrupt entry address determined by VICVectAddr0~15 is determined by the interrupt number (channel, see the chip data sheet for details) represented by the lower 4 bits of VICVectCntl0~15.

Although multiple interrupt sources can be selected (via VICIntSelect) to generate FIQ requests, there is only one dedicated interrupt service routine to service all available/occurring FIQ requests. Therefore, if more than one interrupt is assigned as FIQ, the FIQ interrupt service routine must read the contents of VICFIQStatus to decide how to handle the interrupt request. However, it is recommended to assign only one interrupt as FIQ. Multiple FIQ interrupt sources will increase interrupt latency.

Once a vector IRQ request with interrupt number N is generated, VICVectAddr is the same as the ISR address assigned to interrupt number N, that is, VICVectAddr = VICVectAddr X, and VICVectCnt X = 0X0000 002N, VICVectAddr X = ISR address. Usually, to obtain the ISR address, you can force the ISR function to be converted from void to usigned long, such as VICVectAddr0 = (unsigned long) time_int();

Once a non-vectored IRQ request is generated, the content of VICVectAddr is the same as VICDefVectAddr.

After the interrupt service routine is executed, clearing the peripheral interrupt flag will affect the corresponding bit in the VIC register (VICRawlntr, VICFIQStatus and VICIRQStatus). In addition, in order to service the next interrupt, the ICVectAddr register must be written before the interrupt returns. This write operation will clear the corresponding interrupt flag in the internal interrupt priority hardware.

If the watchdog only generates an interrupt when overflowing or invalid feeding, then there is no way to clear the interrupt. The only way to achieve interrupt return is to disable the VIC interrupt via VICIntEnClr.

VICIRQStatus IRQ status register. This register reads the status of interrupts defined as IRQ and enabled.

VICFIQStatus FIQ Status Request This register reads the status of interrupts defined as FIQ and enabled.

VICRawIntr Status register for all interrupts. This register reads the status of 32 interrupt requests/software interrupts, regardless of whether the interrupt is enabled or classified.

VICIntSelect Interrupt Select Register. This register assigns each of the 32 interrupt requests as FIQ or IRQ

VICIntEnable interrupt enable register. This register controls which of the 32 interrupt requests and software interrupts are enabled as FIQ or IRQ

VICIntEnClr Interrupt Enable Clear Register. This register allows software to clear one or more bits in the Interrupt Enable Register.

VICSoftInt Software interrupt register. The content of this register is “OR” with the interrupt requests of 32 different peripherals.

VICSoftIntClear Software Interrupt Clear Register. This register allows software to clear one or more bits in the Software Interrupt Register.

VICProtection Protection Enable Register. This register allows software running in privileged mode to have limited access to the VIC register. Software running in user mode uses this 1-bit register to control access to the VIC register.

VICVectAddr Vector address register. When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the read address.

VICDefVectAddr Default vector address register. This register stores the interrupt service routine (ISR) address of non-vectored IRQ.

VICVectAddr0~15 Vector address registers 0~15. Vector address registers 0-15 store the interrupt service routine addresses of 16 vector IRQ slots.

VICVectCntl0~15 Vector Control 0~15 registers. Vector Control Registers 0-15 control one of the 16 vector IRQ slots respectively. Slot0 has the highest priority, while Slot15 has the lowest priority. Disabling a vector IRQ slot in the VICVectCntl register does not disable the interrupt itself, the interrupt is simply converted to a non-vectored form.

bit 5 1: Vectored IRQ enable. When the assigned interrupt request or software interrupt enable is assigned as IRQ and declared, a unique interrupt request corresponding to the ISR address can be generated and assigned as FIQ and declared.

Bits 4:0 The interrupt request or software interrupt number assigned to this vectored IRQ slot. As a good programming practice, do not assign the same interrupt number to more than one enabled vectored IRQ slot. However, if you do, when an interrupt request or software interrupt is enabled, assigned to an IRQ and declared, the lowest numbered slot is used. 

The VIC "ORs" all vector and non-vector IRQs to generate an IRQ signal to the ARM processor. The IRQ service routine can be immediately started by reading a register of the VIC and jumps to the corresponding address. If any of the vector IRQs makes a request, the VIC provides the address of the highest priority requesting IRQ service routine, otherwise it provides the address of the default routine. This default routine is shared by all non-vector IRQs. The default routine can read another VIC register to determine which IRQ is activated.

I am learning uCOS-II. When porting to ARM, I consider the definition of data types. However, the definition of data types in Keil MDK compiler is still very vague. The main problem is that I cannot distinguish how many bytes short int, int, long and long int occupy. In order to get an authoritative answer, I use the compiler itself to get it.

1. First, define several variables to store the number of bytes of each data type.

//#include

#include

unsigned char a,b,c,d,e,f,g;

main()

{

   a=sizeof(char);

   b=sizeof(short int);

   c=sizeof(int);

   d=sizeof(long);

   e=sizeof(long int);

   f=sizeof(float);

   g = sizeof(double);

   while(1);

}

    2. Check the storage address of each variable. View---Symbols Window.

3. View the values ​​stored in each address. View---memory Window.

From the above figure, we can see that:

char occupies 1 byte

short int occupies 2 bytes

int occupies 4 bytes

long occupies 4 bytes

long int occupies 4 bytes

float occupies 4 bytes

Double occupies 8 bytes

We can define the macro like this:

typedef unsigned char uint8; // unsigned 8-bit integer variable

typedef signed char int8; // Signed 8-bit integer variable

typedef unsigned short uint16; // unsigned 16-bit integer variable

typedef signed short int16; // signed 16-bit integer variable

typedef unsigned int uint32; // unsigned 32-bit integer variable

typedef signed int int32; // signed 32-bit integer variable

typedef float fp32; // single-precision floating point number (32 bits in length)

typedef double fp64; // Double-precision floating point number (64 bits in length)