Solution to the time error of single chip microcomputer timer interrupt

There are usually several timers inside a single-chip microcomputer. For example, there are timer 0 and timer 1 inside the 8051 single-chip microcomputer. When the timer counts overflow, an interrupt request is sent to the CPU. When the CPU is executing an instruction or an interrupt service program, it often delays responding to the timer overflow interrupt for a period of time. Although this delay has little effect on the low-frequency control system of the single-chip microcomputer, it has a greater impact on the real-time control accuracy of the high-frequency control system of the single-chip microcomputer, and sometimes may cause control accidents. In order to expand the application scope of the single-chip microcomputer, this article introduces the time error between its timer overflow interrupt and the CPU response interrupt, as well as the method and example of compensating the error.

2 Causes, size and characteristics of errors

There are two reasons for the time difference between the MCU timer overflow interrupt and the CPU response interrupt. One is that the CPU is executing an instruction when the timer overflow interrupt signal is issued; the other is that the CPU is executing an interrupt service program when the timer overflow interrupt signal is issued.

2.1. Error and size when the CPU is executing a certain instruction

Because the CPU is executing an instruction, it cannot respond to the overflow interrupt of the timer in time. The longest delay time for the CPU to respond to the interrupt after executing this instruction is the instruction cycle of the instruction, that is, the maximum value of the error is the time required to execute the instruction. Since each instruction has a corresponding instruction cycle, this error will vary depending on the instruction the CPU is executing. For example, when the timer overflows and the interrupt occurs, the CPU is executing the instruction MOV A, Rn, and its maximum error is 1 machine cycle. When executing the instruction MOV Rn, direct, its maximum error is 2 machine cycles. When the CPU is executing a multiplication or division instruction, the maximum time error can reach 4 machine cycles. In the 8051 single-chip microcomputer instruction system, the instruction cycle of most instructions is 1 to 2 machine cycles, so the maximum time error is generally 1 to 2 machine cycles. If the oscillator oscillation frequency is fosc, and the number of machine cycles of the CPU executing the instruction is Ci, then the maximum time error is Δtmax1=12/fosc×Ci(us). For example, fosc=12MHZ, the CPU is executing a multiplication instruction (Ci=4), and the maximum time error at this time is:

Δtmax1=12/fosc×Ci=12/(12×106)×4=4×10-6(s)=4(μs)

2.2 Error and size when the CPU is executing an interrupt service program

When the timer overflows the interrupt signal, if the CPU is executing the same-level or high-priority interrupt service program, it still needs to continue to execute these programs and cannot respond to the timer overflow interrupt request in time. The delay time is composed of the interrupt transfer instruction cycle T1, the interrupt service program execution time T2, the interrupt return instruction instruction cycle T3, and the next instruction cycle T4 (such as multiplication instruction) after the interrupt returns to the original breakpoint. The instruction cycles of the interrupt transfer instruction and the interrupt return instruction are 2 machine cycles respectively. The execution time of the interrupt service program is the sum of the instruction cycles of the instructions contained in the program. Therefore, the maximum time error Δtmax2 is:

Δtmax2=(T1+T2+T3+T4)12/fosc=(2+T2+2+4)12/ fosc=12(T2+8)/ fosc

If fosc=12MHZ, the maximum time error is:

Δtmax2=12(T2+8)/fosc =12(T2+8)/12×106=(T2+8)×10-6(s)=T2+8(μs).

Since T2 in the above formula is generally greater than 8, this time error generally depends on the interrupt service program being executed. When the CPU is executing the interrupt return instruction RETI, or reading or writing the IE or IP instruction, this error is within 5 machine cycles.

2.3 Error non-fixed characteristics

The time error between the timer overflow interrupt and the CPU response interrupt is non-fixed. That is, this error varies greatly depending on the instruction the CPU is executing. If the CPU is executing an interrupt service program, this error will be much greater than the error when executing an instruction. The latter error may be several times, dozens of times, or even greater than the former error. If only one instruction is executed, this error will also be quite different. For example, the time error of executing the multiplication instruction MUL AB increases by 3 machine cycles compared to executing the MOV A, Rn instruction. The non-fixedness of this error not only brings inconvenience to error analysis, but also brings difficulties to error compensation.
 

3 Error compensation method

Since the time difference between the timer overflow interrupt and the CPU responding to the interrupt request is not fixed, it is difficult to compensate for this error using conventional methods. Therefore, this article introduces a new method. The basic idea of ​​this method, the new initial value of the timer, and its application are introduced below.

3.1 Basic Idea

In order to synchronize the timer overflow interrupt with the CPU response interrupt, this method modifies the original count initial value of the timer according to the time error between the interrupt response and the interrupt request, so as to extend the timer counting time and compensate for the error. In this method, when the timer overflow interrupt is responded, the timer counting is stopped and the count value is read out. The count value is the value counted by adding 1 every machine cycle starting from OOH after the timer overflows. Then, this value is summed with the stop counting time of the timer. If this sum is subtracted from the original count initial value of the timer to form a new count initial value, the timer can synchronize the overflow interrupt with the CPU response interrupt under the new count initial value, thereby achieving the error compensation requirement.

3.2 New initial value of timer count

If the timer is in counting mode and the operation mode is 1, the initial value of the counter X0 = 216-t0×fosc/12. In the formula, fosc is the oscillation frequency of the oscillator. t0 is the time required for timing, which is also the interval time of the interrupt. X0 is the original initial value of the timer. When compensating for the time error between the timer overflow interrupt and the CPU response interrupt, the new initial value of the timer X1 is:

X1=216-t3×fosc/12

t3=t0+t1+t2

Where t0 is the interrupt interval time. t1 is the time when the timer stops counting, which is the sum of all program instruction cycles between the timer stopping counting and restarting counting. t2 is the value of the timer counting from OOH to the timer stopping after the timer overflow interrupt. In error compensation, if the timer count initial value X1 replaces X0, the next overflow interrupt of the timer can be synchronized with the CPU response interrupt.

3.3 Examples

It is required to compensate for the error of interrupt response delay when the timer generates an overflow interrupt every 1ms. If the oscillator oscillation frequency fosc = 12MHZ, the timer works in counting mode, and the working mode is 1, then the new initial value X1 of the timer when compensating for the interrupt response time error is:

X1=216-t3× fosc/12=216-(t0+ t1)- t2=216-(1000+ 13)- t2

The error compensation procedure is:

…

0 CLR EA ; Disable CPU interrupt

1 CLR TRi ; Stop timer counting

2 MOV R0, #OOH; R0 is cleared

3 MOV R0, #LOW(216); the lower 8 bits of the maximum count value of the timer are sent to R0

4 MOV A, R0
 

5 SUBB A, #LOW(1000+13); Subtract the lower 8 bits of (t0+t1) from the lower 8 bits of 216 and send to accumulator A

6 SUBB A, TLi; Subtract the lower 8 bits of (t0+t1+t2) from the lower 8 bits of 216 and send to TLi

7 MOV TLi， A

8 MOV R0, #OOH; R0 is cleared

9 MOV R0, #HIGH(216); the high 8 bits of 216 are sent to R0

10 MOV A，R0

11 SUBB A, #HIGH(1000+13); Subtract the high 8 bits of 216 from the high 8 bits of (t0+t1) and send to A

12 SUBB A, THi ; Subtract the high 8 bits of (t0+ t1 +t2) from the high 8 bits of 216 and send to A

13 MOV THi， A

14 SETB TRi ; Restart timer

…

In the above formula and the previous program, since fosc=12MHZ and the interrupt interval is 1ms, the machine cycle number of t0 is 1000. Since the sum of the machine cycle numbers of the instruction cycles from the 1st instruction to the 14th instruction is 13, t1 is 13 machine cycles. Although the CPU stops the timer counting after executing the first instruction CLR TRi, the low-order data and high-order data of t2 are saved in TLi and THi respectively.

4 Conclusion

Since the error compensation method introduced in this paper can effectively compensate for the non-fixed time error between the timer overflow interrupt and the CPU response interrupt, this method has high practical value for improving the real-time control accuracy of high-frequency control systems and expanding the application scope of single-chip microcomputers.