Research and implementation of UAV flight control system based on ARM

    The UAV flight control system is a comprehensive system with high-performance autonomous navigation, automatic flight control, and mission management, which requires a large amount of complex data processing and mathematical operations. The flight control computer is the core subsystem of the flight control system. With the development of aerospace technology, the flight control computer is developing towards high precision and miniaturization. High precision requires the guidance and control of the UAV to have high precision and good stability, and to be able to adapt to complex external environments, resulting in more complex control algorithms, fast calculation speed, and high precision. Miniaturization puts higher requirements on the weight and volume of the control system, requiring the computer to have the highest performance and the smallest volume. Performance indicators and volume restrictions urgently require the development of new flight control computers.

2. Design requirements for the interface between the flight control computer and the peripherals

The key to the design of an ARM-based flight control computer lies in the overall system design. Interface design is an important link, and its quality will directly affect the performance of the system. Anti-interference should be considered when inputting and outputting signals. The overall solution designed should be easy to implement and have a certain adaptability to different types of drones. For models with similar requirements, the control software should be modified, and the hardware design should be modified less or not at all. These requirements should be considered in all aspects of the design.

First, we need to analyze the flight control/navigation tasks and goals of the drone. According to the flight requirements and the complexity of the control object, we can select the control cycle; according to the amount of control calculations within the control cycle, we can determine the type of calculation and the speed of operation; and in combination with the external unit, we can determine the interface solution and the consideration of anti-interference factors to determine the overall communication protocol and interface form.

During the flight of a drone, in order to achieve certain flight missions, it is necessary to control its flight attitude and guide the aircraft to fly accurately along a certain route. In order to perform attitude control, it is necessary to obtain real-time parameter information of the flight attitude and remote control telemetry parameters. With these information parameters, after the computer control algorithm calculates, the control grain is output to the actuator in real time, thereby achieving the control/navigation purpose. The schematic diagram of its composition is shown in Figure 1.

The vertical gyro and three-axis angular rate gyro output analog signals, so the flight control computer must have the ability to collect multiple analog signals with high precision. The data exchange between the magnetic heading sensor, altitude sensor, and peripheral units such as GPS and remote control telemetry uses RS-485 and RS-232 communication protocols, so the flight control computer must have the ability to pass multiple serial ports. At the same time, the system requires a series of level output/input interfaces, servo interfaces, and other interfaces.

1. ARM’s choice

Considering the calculation accuracy, calculation speed, control performance requirements, power consumption and the above interfaces, the AT91M55800A chip of ATMEL is used as the CPU. This chip integrates the ARM7TDMI core, embedded ICE interface, memory and peripherals.

AT91M55800A具有先进系统总线(ASB)和先进外围总线(APB)两条主要总线，ASB接口由存储控制寄存器控制用于实现最高的性能。ARM7TDMI核通过ASB接口实现与片内32位存储器、外部总线接口(EBI)以及AMBA桥的连接。AMBA桥用来驱动APB；APB用来访问片内外围，优化系统功耗AT91M55800A通过完全可编程的外部总线接口直接连到片外存储器，使读或写操作最快可达一个时钟周期。8优先级向量中断控制器和片内外围数据控制器则显著提高了器件的实时性能.

The main hardware resources and key features of AT91M55800A are as follows:

(1) The chip provides abundant on-chip resources. With on-chip A/D and D/A converters, the system does not need external A/D and D/A chips, which improves system reliability and reduces system complexity. The AT91M55800A has an on-chip watchdog circuit that can monitor accidental program runaway. The AT91M55800A chip provides an SPI bus for easy connection with expansion peripherals.

    (2) Integrates the ARM7TDMI ARM Thumb processing core - a low-power, high-performance 32-bit RISC (Reduced Instruction Set Computer) processor. It has powerful instruction functions, adopts a three-stage pipeline and von Neumann architecture that can provide 0.9MIPS/MHz; has an enhanced multiplier that can produce 64-bit results; has strong addressing capabilities, has ARM instruction sets and Thumb instruction sets; embedded ICE, advanced software development and debugging

Test environment.

    (3) 8KB on-chip SRAM.—32-bit data bus width, single clock cycle access.

    (4) Fully programmable external bus interface (EBI) - maximum addressable space is 64MB, up to 8 chip select lines, software programmable 8-bit or 16-bit external data bus.

    (5) 8-priority, individually maskable vectored interrupt controller (AIC) - 7 external interrupts, including one high-priority, low-latency interrupt request.

    (6) 58 programmable I/O lines controlled by PIOA and PIOB.

    (7) 6-channel 16-bit timer/counter, real-time clock (RTC), system timer, watchdog timer.

    (8) Master-slave SPI interface—8~16 bits programmable data length, 4 external slave chip selects.

    (9) Real clock using on-chip master oscillator and PLL multiplier clock generator and on-chip 32K oscillator - 3MHz~33MHz frequency range.

    (10) Has 3 USARTs—each USART has two peripheral data controller (PDC) channels.

    (11) 8-channel 10-bit ADC and 2-channel 10-bit DAC.

    (12) Advanced Power Management Controller (APMC)—Normal, Wait, Slow, Standby, and Power-off modes.

    (13) JEEE 1149.1 JTAG boundary scan for all digital pins.

The above functions and features of AT91M55800A enable complex control algorithms to be completed within the specified time and meet the accuracy requirements.

2. Memory expansion

Since the internal memory of AT91M55800A is small, most of the programs and data can only be placed outside the chip, so memory expansion is required. The core of AT91M55800A adopts the von Neumann structure. The memory interface can realize its potential with the least memory usage. The speed-critical control signals are processed in a pipeline operation with extremely fast processing speed. The speed of the selected RAM must be less than the read and write cycle of the RAM. When the system is working, the program must be placed in the Flash, and when the system is powered on, the startup code program is moved to the off-chip RAM for operation. Therefore, the storage capacity and speed must also be considered when selecting ROM. According to the above characteristics, a 12ns IS61LV51216RAM is selected to form the RAM of the storage system, and a 90ns access cycle AT49BV1604A-90TI (Flash Memory) is selected as the program storage space. In addition, an X5045 (NOVRAM) is expanded through the SPI bus. NOVRAM can save the set track and mission data after power failure.

3. Receiving analog signals

The analog signals output by the vertical gyro, angular rate gyro, power supply voltage, etc. are first input through the signal conditioning module. The 8-channel 10-bit ADC on the chip has fully met the requirements of the number of system channels and accuracy, and no other ADC devices are needed. The collected signals such as aircraft attitude and grid voltage are the basis for the flight control system to control and monitor the working status of the UAV. At the same time, these signals are encoded and sent to the ground telemetry equipment for reference by the operator.

4. Serial communication

Most of the output signals of the sensors on board are in serial standard. Remote control commands, telemetry data, GPS data, altitude signals, heading signals, route setting, and control parameter settings all use RS-232 or RS-485 interfaces, but the three USARTs integrated in the AT91M55800A chip cannot meet the requirements, and the serial port must be expanded. Using software simulation to expand the serial port will increase the processor load and reduce the real-time performance of the system. Using the 16C554 dedicated serial port expansion chip will increase the circuit complexity of the system and increase the circuit board area. After considering various solutions, the serial port is configured as follows:

(1) Serial port 0 is the remote control channel, which is connected to the remote control receiver, receives the remote control information sent from the uplink channel, and transmits the aircraft status parameter information downlink. It is RS-232 standard with a baud rate of 9600.

(2) Serial port 1: connected to the altitude sensor and heading sensor through 4052 expansion. Adopts RS-485 standard, baud rate 9600.

(3) Serial port 2 is connected to the GPS receiver to receive GPS data, using the RS-232 standard with a baud rate of 9600.

(4) The USART transceiver device MAX3111 with SPI bus interface has expanded a serial interface. The TX channel of this serial port is used as a telemetry channel to send telemetry information such as flight attitude, power supply voltage, engine speed, and mission equipment working status; the RX channel is dual-purpose and can be used to set the preset route for autonomous flight and to set control parameters. In this way, both the real-time and compactness of the system are taken into account.

5. Output of frequency signal

Four servos are commonly used to control servo mechanisms. During flight, these four servos must be able to operate simultaneously without any delay between them. The 6-way timer/counter of AT91M55800A can be used as a device to output PWM signals, without the need to expand the interface chip. The remaining timer is used as the system clock of μC/OS-II, and the other timer is used to monitor the engine speed. According to the working mode and control accuracy requirements of the servo, the working mode is set to meet the working requirements of the servo. This reduces both hardware expansion and software consumption, improves accuracy, and greatly improves system efficiency.

6. Digital I/O port output

     The on-chip PIOA and PIOB controllers output switching quantities through the AT91M55800A GI/O, and control mission equipment, recovery devices, and other equipment through optocoupler isolation and driver amplification.

7. Reset circuit

     When AT91M55800A is reset, the main clock comes from the slow clock (32 768Hz), and the signal on the main clock must remain valid for at least 10 clock cycles before the rising edge of the NRST signal, and the reset signal must remain valid for at least 0.3ms. The reset time of the extended storage system is less than 0.3ms, so this system uses the MAX6315 chip that can provide a 20ms low pulse. At the same time, AT91M55800A has a programmable watchdog timer. When the system cannot work due to a momentary lack of system power or an accidental power failure, causing the program to run away or important data to be lost, the watchdog timer can generate an internal reset signal to reset the system.

4. Key technologies in system design

1. Principles of rational use of hardware resources and port configuration

AT91M55800A has abundant hardware resources. Whether these resources can be fully utilized and properly configured is the key to the success of the design. If the CPU is overloaded, the system may find it difficult to complete the task of real-time control. If the configuration is unreasonable, the resources cannot be fully utilized, and it will affect the real-time performance of the system and increase the complexity of the software. The CPU mainly processes 4 analog inputs, 10 switch inputs, 1 frequency input, 3 timing signal inputs, 4 PWM wave outputs, 8 switch outputs and 4 serial data interfaces. They are configured according to the structural characteristics of the microcontroller, such as configuring the analog input in the A/D part, the switch input and output in the GPI/O, the 3 timing signal inputs, 1 frequency input and PWM wave in the timer/counter multi-channel part, and the 4 serial data interfaces are configured on 3 USARTs through appropriate expansion. In the design, the following principles are followed for port allocation, and certain time calculations are made;

(1) First, determine the implementation scheme of the MCU core to create conditions for determining the input and output signal connection scheme;

    (2) Give priority to the basic functions of each port, and then consider the secondary and tertiary functions of the port;

    (3) Consider signal matching and port driving capability;

    (4) Considering the time factor, estimate and calculate the time of ADC, UARST, GPI/O, PWM, SPI and other processing subroutines to determine the CPU task load and ensure that the CPU has a certain time margin;

    (5) Use spare ports for redundant design to allow a certain degree of freedom in the implementation of certain functions.

2. Anti-interference measures of the system

Among the various performance indicators of drone systems, reliability is the primary factor to consider. The drone flight controller must operate stably and reliably, otherwise it will lead to control deviations, which may cause huge economic losses or life-threatening situations. Therefore, in the design of the controller hardware, the principle of high reliability and high stability must be always implemented, and a good foundation must be laid for the implementation of software anti-interference measures.

The main factors that affect the reliable and safe operation of the controller are the following: electromagnetic field interference, power supply method, component performance, PCB layout and routing, mechanical structure design, etc.

In view of these factors, the following measures are adopted in the hardware design of this system:

(1) The main control board uses a four-layer high-frequency circuit board;

    (2) Use filtering technology, decoupling capacitors, shielding technology, isolation technology and grounding technology to reduce electromagnetic field interference;

    (3) Independent power supply for digital and analog parts

(4) Try to use surface mount components with high integration, high stability and high reliability;

    (5) Components on the PCB are divided into functional areas, arranged nearby, with 45° routing and full grounding;

    (6) Select high-reliability connectors, secure installation, and shielded housing.

3. Considerations of power supply and power consumption of the whole machine

The power source of the drone is the onboard battery with limited energy, so the energy consumption is an indicator to measure its performance. The onboard battery provides a ±12V DC power supply. For the flight controller, two problems need to be solved. The first is how to perform DC/DC conversion to meet the system's requirements for power quantity and voltage value, and make the conversion efficiency high enough; the second is what kind of components to choose to meet the signal matching requirements and make the device power consumption low.

The system uses a small PKC2121 module with high conversion efficiency, which can generate a stable ±12V voltage to provide input for the ±9V power reference. 5V and 9V are used to power the analog circuit according to specific needs. 5V is used as the input voltage of the 3.3V power reference REF192GS, and 3.3V is used to power the flight control computer and storage system. Under the premise of signal matching, low-power CMOS devices are used as much as possible to reduce the total energy consumption of the system.

V. Conclusion

After preliminary debugging, all functions of the hardware platform have achieved the design purpose. In order to facilitate the joint debugging with the hardware, the software design uses the real-time embedded operating system μC/OS-II with open source code as the software platform, and divides the system functions into data acquisition module, control solution module, modal control module, altitude and heading reading module, instruction receiving module, GPS receiving module, route control module, telemetry sending module, and assembly language is used for the chip startup part. For complex algorithms and large calculations, C language is used. After the software and hardware are debugged separately, the software and hardware can be jointly debugged, and finally a new flight control computer based on ARM is formed.

The hardware system is small in size and low in cost. The design adopts a modular structure, separating the main control module from the signal conditioning module and the signal output module. Then, the combination of the main control module with different signal conditioning modules and output signals can realize the versatility of the design system as a flight controller for a series of drones of a certain model. With the continuous development of technology, ARM will be widely used in military and high-tech with its unique advantages.

references:

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[5] Ma Zhongmei et al. ARM Embedded Processor Architecture and Application Basics[M]. Beijing: Beijing University of Aeronautics and Astronautics Press. 2003